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XC2V4000-4BF957C 参数 Datasheet PDF下载

XC2V4000-4BF957C图片预览
型号: XC2V4000-4BF957C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Virtex -II 1.5V的现场可编程门阵列 [Virtex-II 1.5V Field-Programmable Gate Arrays]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 7 页 / 128 K
品牌: XILINX [ XILINX, INC ]
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Virtex-II 1.5V
Field-Programmable Gate Arrays
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DS031-1 (v1.7) October 2, 2001
Advance Product Specification
Summary of Virtex
®
-II Features
Industry First Platform FPGA Solution
IP-Immersion™ Architecture
- Densities from 40K to 8M system gates
- 420 MHz internal clock speed (Advance Data)
- 840+ Mb/s I/O (Advance Data)
SelectRAM™ Memory Hierarchy
- 3 Mb of True Dual-Port™ RAM in 18-Kbit block
SelectRAM resources
- Up to 1.5 Mb of distributed SelectRAM resources
- High-performance interfaces to external memory
·
DDR-SDRAM interface
·
FCRAM interface
·
QDR™-SRAM interface
·
Sigma RAM interface
Arithmetic Functions
- Dedicated 18-bit x 18-bit multiplier blocks
- Fast look-ahead carry logic chains
Flexible Logic Resources
- Up to 93,184 internal registers / latches with Clock
Enable
- Up to 93,184 look-up tables (LUTs) or cascadable
16-bit shift registers
- Wide multiplexers and wide-input function support
- Horizontal cascade chain and Sum-of-Products
support
- Internal 3-state bussing
High-Performance Clock Management Circuitry
- Up to 12 DCM (Digital Clock Manager) modules
·
Precise clock de-skew
·
Flexible frequency synthesis
·
High-resolution phase shifting
- 16 global clock multiplexer buffers
Active Interconnect™ Technology
- Fourth generation segmented routing structure
- Predictable, fast routing delay, independent of
fanout
SelectI/O-Ultra™ Technology
- Up to 1,108 user I/Os
- 19 single-ended standards and six differential
standards
- Programmable sink current (2 mA to 24 mA) per I/O
Digitally Controlled Impedance (DCI) I/O: on-chip
termination resistors for single-ended I/O standards
- PCI-X @ 133 MHz, PCI @ 66 MHz and 33 MHz
compliance, and CardBus compliant
- Differential Signaling
·
840 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers
·
Bus LVDS I/O
·
Lightning Data Transport (LDT) I/O with current
driver buffers
·
Low-Voltage Positive Emitter-Coupled Logic
(LVPECL) I/O
·
Built-in DDR Input and Output registers
- Proprietary high-performance SelectLink™
Technology
·
High-bandwidth data path
·
Double Data Rate (DDR) link
·
Web-based HDL generation methodology
Supported by Xilinx Foundation™ and Alliance™
Series Development Systems
- Integrated VHDL and Verilog design flows
- Compilation of 10M system gates designs
- Internet Team Design (ITD) tool
SRAM-Based In-System Configuration
- Fast SelectMAP™ configuration
- Triple Data Encryption Standard (DES) security
option (Bitstream Encryption)
- IEEE1532 support
- Partial reconfiguration
- Unlimited re-programmability
- Readback capability
0.15 µm 8-Layer Metal process with 0.12 µm
high-speed transistors
1.5 V (V
CCINT
) core power supply, dedicated 3.3 V
V
CCAUX
auxiliary and V
CCO
I/O power supplies
IEEE 1149.1 compatible boundary-scan logic support
Flip-Chip and Wire-Bond Ball Grid Array (BGA)
packages in three standard fine pitches (0.80mm,
1.00mm, and 1.27mm)
100% factory tested
-
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS031-1 (v1.7) October 2, 2001
Advance Product Specification
1-800-255-7778
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