R
XC3000 Series Field Programmable Gate Arrays
testing, no soft errors have been observed even in the
presence of very high doses of alpha radiation.
Q
Q
Configuration
Control
The method of loading the configuration data is selectable.
Two methods use serial data, while three use byte-wide
data. The internal configuration logic utilizes framing infor-
mation, embedded in the program data by the development
system, to direct memory-cell loading. The serial-data
framing and length-count preamble provide programming
compatibility for mixes of various FPGA device devices in a
synchronous, serial, daisy-chain fashion.
Read or
Write
Data
X5382
Figure 3: Static Configuration Memory Cell.
It is loaded with one bit of configuration program and con-
trols one program selection in the Field Programmable
Gate Array.
I/O Block
Each user-configurable IOB shown in Figure 4, provides an
interface between the external package pin of the device
and the internal user logic. Each IOB includes both regis-
tered and direct input paths. Each IOB provides a program-
mable 3-state output buffer, which may be driven by a
registered or direct output signal. Configuration options
allow each IOB an inversion, a controlled slew rate and a
high impedance pull-up. Each input circuit also provides
input clamping diodes to provide electrostatic protection,
and circuits to inhibit latch-up produced by input currents.
The memory cell outputs Q and Q use ground and V lev-
CC
els and provide continuous, direct control. The additional
capacitive load together with the absence of address
decoding and sense amplifiers provide high stability to the
cell. Due to the structure of the configuration memory cells,
they are not affected by extreme power-supply excursions
or very high levels of alpha particle radiation. In reliability
Vcc
PROGRAM-CONTROLLED MEMORY CELLS
7
OUT
INVERT
OUTPUT
SELECT
SLEW
RATE
PASSIVE
PULL UP
3-STATE
INVERT
T
3- STATE
(OUTPUT ENABLE)
O
D
Q
OUTPUT
BUFFER
OUT
FLIP
FLOP
I/O PAD
R
I
DIRECT IN
Q
REGISTERED IN
Q
D
FLIP
TTL or
CMOS
INPUT
FLOP
or
LATCH
THRESHOLD
R
(GLOBAL RESET)
OK
IK
CK1
CK2
PROGRAM
CONTROLLED
MULTIPLEXER
=
PROGRAMMABLE INTERCONNECTION POINT or PIP
X3029
Figure 4: Input/Output Block.
Each IOB includes input and output storage elements and I/O options selected by configuration memory cells. A choice
of two clocks is available on each die edge. The polarity of each clock line (not each flip-flop or latch) is programmable.
A clock line that triggers the flip-flop on the rising edge is an active Low Latch Enable (Latch transparent) signal and vice
versa. Passive pull-up can only be enabled on inputs, not on outputs. All user inputs are programmed for TTL or CMOS
thresholds.
November 9, 1998 (Version 3.1)
7-7
XILINX [ XILINX, INC ]
