R
Spartan-3 1.2V FPGA Family: Functional Description
Table 7: DCI Terminations
Termination
Schematic(1)
I/O Standards
LVDCI_15
Controlled impedance output driver
IOB
LVDCI_18
LVDCI_25
LVDCI_33
R
Z
0
Controlled output driver with half impedance
LVDCI_DV2_15
LVDCI_DV2_18
LVDCI_DV2_25
LVDCI_DV2_33
IOB
R/2
Z
0
Single resistor
GTL_DCI
V
CCO
IOB
GTLP_DCI
HSTL_III_DCI(2)
HSTL_III_DCI_18(2)
R
Z
0
Split resistors
HSTL_I_DCI(2)
V
CCO
IOB
HSTL_I_DCI_18(2)
HSTL_II_DCI_18
LVDS_25_DCI
2R
Z
0
LVDSEXT_25_DCI
2R
Split resistors with output driver impedance
fixed to 25Ω
SSTL18_I_DCI(3)
SSTL2_I_DCI(3)
SSTL2_II_DCI
V
CCO
IOB
25Ω
2R
2R
Z
0
Notes:
1. The value of R is equivalent to the characteristic impedance of the line connected to the I/O. It is also equal to half the value of RREF
for the DV2 standards and RREF for all other DCI standards.
2. For DCI using HSTL Classes I and III, terminations only go into effect at inputs (not at outputs).
3. For DCI using SSTL Class I, the split termination only goes into effect at inputs (not at outputs).
DS099-2 (v1.2) July 11, 2003
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