R
Functional Description
T
TFF1
D
T1
Q
CE
CK
SR REV
DDR
MUX
TCE
T2
D
Q
TFF2
CE
CK
SR REV
Three-state Path
ODDROUT1
V
CCO
OFF1
O1
ODDRIN1
OTCLK1
D
Q
CE
CK
Pull-Up
ESD
ESD
SR REV
DDR
MUX
I/O
Pin
OCE
Program-
Pull-
Down
O2
mable
Output
Driver
Q
D
OFF2
ODDRIN2
CE
CK
OTCLK2
SR REV
Keeper
Latch
Output Path
ODDROUT2
I
LVCMOS, LVTTL, PCI
IQ1
Programmable
Delay
IDDRIN1
IDDRIN2
D
Q
Single-ended Standards
using V
IFF1
REF
CE
V
REF
Pin
ICLK1
ICE
CK
SR REV
Differential Standards
IQ2
I/O Pin
from
Adjacent
IOB
D
Q
IFF2
CE
CK
ICLK2
SR REV
SR
REV
Input Path
DS312-2_19_030105
Notes:
1. All IOB signals communicating with the FPGA’s internal logic have the option of inverting polarity inside the IOB.
2. Signals shown with dashed lines connect to the adjacent IOB in a differential pair only, not to the FPGA fabric.
Figure 1: Simplified IOB Diagram
2
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
XILINX [ XILINX, INC ]
