R
XC4000E and XC4000X Series Field Programmable Gate Arrays
4
C1 • • • C4
WE
D1
D0
EC
DIN
WRITE
DECODER
G1 • • • G4
4
4
1 of 16
LATCH
ENABLE
16-LATCH
ARRAY
MUX
G'
WRITE PULSE
READ
ADDRESS
DIN
WRITE
DECODER
F1 • • • F4
4
4
1 of 16
LATCH
ENABLE
16-LATCH
ARRAY
MUX
F'
K
(CLOCK)
WRITE PULSE
READ
ADDRESS
X6752
Figure 4:
16x2 (or 16x1) Edge-Triggered Single-Port RAM
C1 • • • C4
4
EC
WE
D1/A4
D0
EC
DIN
WRITE
DECODER
G1 • • • G4
F1 • • • F4
4
4
1 of 16
LATCH
ENABLE
16-LATCH
ARRAY
MUX
G'
WRITE PULSE
READ
ADDRESS
H'
DIN
WRITE
DECODER
4
4
1 of 16
LATCH
ENABLE
16-LATCH
ARRAY
MUX
F'
K
(CLOCK)
WRITE PULSE
READ
ADDRESS
X6754
Figure 5: 32x1 Edge-Triggered Single-Port RAM (F and G addresses are identical)
6-14
May 14, 1999 (Version 1.6)