欢迎访问ic37.com |
会员登录 免费注册
发布采购

XC95108-10TQ100C 参数 Datasheet PDF下载

XC95108-10TQ100C图片预览
型号: XC95108-10TQ100C
PDF下载: 下载PDF文件 查看货源
内容描述: XC95108在系统可编程CPLD [XC95108 In-System Programmable CPLD]
分类和应用: 可编程逻辑器件输入元件
文件页数/大小: 8 页 / 72 K
品牌: XILINX [ XILINX, INC ]
 浏览型号XC95108-10TQ100C的Datasheet PDF文件第2页浏览型号XC95108-10TQ100C的Datasheet PDF文件第3页浏览型号XC95108-10TQ100C的Datasheet PDF文件第4页浏览型号XC95108-10TQ100C的Datasheet PDF文件第5页浏览型号XC95108-10TQ100C的Datasheet PDF文件第6页浏览型号XC95108-10TQ100C的Datasheet PDF文件第7页浏览型号XC95108-10TQ100C的Datasheet PDF文件第8页  
1
®
XC95108 In-System Programmable
CPLD
1
1*
December 4, 1998 (Version 3.0)
Product Specification
Features
7.5 ns pin-to-pin logic delays on all pins
f
CNT
to 125 MHz
108 macrocells with 2400 usable gates
Up to 108 user I/O pins
5 V in-system programmable (ISP)
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs
3.3 V or 5 V I/O capability
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 84-pin PLCC, 100-pin PQFP, 100-pin TQFP
and 160-pin PQFP packages
Power Management
Power dissipation can be reduced in the XC95108 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
I
CC
(mA) =
MC
HP
(1.7) + MC
LP
(0.9) + MC (0.006 mA/MHz) f
Where:
MC
HP
= Macrocells in high-performance mode
MC
LP
= Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
shows a typical calculation for the XC95108
device.
300
High P
Typical I
CC
(mA)
anc
erform
e
(250)
200
(180)
Low P
ower
(170)
Description
The XC95108 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of six
36V18 Function Blocks, providing 2,400 usable gates with
propagation delays of 7.5 ns. See
for the architec-
ture overview.
100
0
50
Clock Frequency (MHz)
100
X5898
Figure 1: Typical I
CC
vs. Frequency for XC95108
December 4, 1998 (Version 3.0)
1