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XC95216-15HQ208C 参数 Datasheet PDF下载

XC95216-15HQ208C图片预览
型号: XC95216-15HQ208C
PDF下载: 下载PDF文件 查看货源
内容描述: XC95216在系统可编程CPLD [XC95216 In-System Programmable CPLD]
分类和应用: 可编程逻辑器件输入元件时钟
文件页数/大小: 10 页 / 66 K
品牌: XILINX [ XILINX, INC ]
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1
XC95216 In-System Programmable
CPLD
1
0*
August 21, 2001 (Version 3.1)
Product Specification
Features
10 ns pin-to-pin logic delays on all pins
f
CNT
to 111 MHz
216 macrocells with 4800 usable gates
Up to 166 user I/O pins
5 V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs
3.3 V or 5 V I/O capability
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 160-pin PQFP, 352-pin BGA, and 208-pin
HQFP packages
Power Management
Power dissipation can be reduced in the XC95216 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
I
CC
(mA) =
MC
HP
(1.7) + MC
LP
(0.9) + MC (0.006 mA/MHz) f
Where:
MC
HP
= Macrocells in high-performance mode
MC
LP
= Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1
shows a typical calculation for the XC95216
device.
600
erform
High P
ance
(500)
Typical I
CC
(mA)
400
(360)
(340)
Description
The XC95216 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of twelve
36V18 Function Blocks, providing 4,800 usable gates with
propagation delays of 10 ns. See
Figure 2
for the architec-
ture overview.
Low
200
Power
0
50
Clock Frequency (MHz)
100
X5918
Figure 1: Typical I
CC
vs. Frequency For XC95216
August 21, 2001 (Version 3.1)
1