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XC9536-7VQ44C 参数 Datasheet PDF下载

XC9536-7VQ44C图片预览
型号: XC9536-7VQ44C
PDF下载: 下载PDF文件 查看货源
内容描述: XC9536在系统可编程CPLD [XC9536 In-System Programmable CPLD]
分类和应用:
文件页数/大小: 7 页 / 63 K
品牌: XILINX [ XILINX, INC ]
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9
1
®
XC9536 In-System Programmable
CPLD
1
1*
December 4, 1998 (Version 5.0)
Product Specification
Features
5 ns pin-to-pin logic delays on all pins
f
CNT
to 100 MHz
36 macrocells with 800 usable gates
Up to 34 user I/O pins
5 V in-system programmable (ISP)
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs
3.3 V or 5 V I/O capability
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 44-pin PLCC, 44-pin VQFP, and 48-pin
CSP packages
Power Management
Power dissipation can be reduced in the XC9536 by config-
uring macrocells to standard or low-power modes of opera-
tion. Unused macrocells are turned off to minimize power
dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
I
CC
(mA) =
MC
HP
(1.7) + MC
LP
(0.9) + MC (0.006 mA/MHz) f
Where:
MC
HP
= Macrocells in high-performance mode
MC
LP
= Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
shows a typical calculation for the XC9536 device.
ance
erform
High P
(83)
Typical I
CC
(mA)
(50)
(50)
Low P
(30)
ower
Description
The XC9536 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of two
36V18 Function Blocks, providing 800 usable gates with
propagation delays of 5 ns. See
for the architec-
ture overview.
0
50
Clock Frequency (MHz)
100
X5920
Figure 1: Typical I
CC
vs. Frequency For XC9536
December 4, 1998 (Version 5.0)
1