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XC9572-10PC44C 参数 Datasheet PDF下载

XC9572-10PC44C图片预览
型号: XC9572-10PC44C
PDF下载: 下载PDF文件 查看货源
内容描述: XC9572在系统可编程CPLD [XC9572 In-System Programmable CPLD]
分类和应用: 可编程逻辑器件输入元件时钟
文件页数/大小: 8 页 / 67 K
品牌: XILINX [ XILINX, INC ]
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1
®
XC9572 In-System Programmable
CPLD
1
1*
December 4, 1998 (Version 3.0)
Product Specification
Features
7.5 ns pin-to-pin logic delays on all pins
f
CNT
to 125 MHz
72 macrocells with 1,600 usable gates
Up to 72 user I/O pins
5 V in-system programmable (ISP)
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs
3.3 V or 5 V I/O capability
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP
and 100-pin TQFP packages
Power Management
Power dissipation can be reduced in the XC9572 by config-
uring macrocells to standard or low-power modes of opera-
tion. Unused macrocells are turned off to minimize power
dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
I
CC
(mA) =
MC
HP
(1.7) + MC
LP
(0.9) + MC (0.006 mA/MHz) f
Where:
MC
HP
= Macrocells in high-performance mode
MC
LP
= Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
shows a typical calculation for the XC9572 device.
200
erform
High P
Typical I
cc
(ma)
a n ce
(160)
(125)
100
o we r
Low P
(100)
Description
The XC9572 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of four
36V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 7.5 ns. See
for the architec-
ture overview.
(65)
0
50
Clock Frequency (MHz)
100
Figure 1: Typical I
CC
vs. Frequency for XC9572
December 4, 1998 (Version 3.0)
1