XC9572 In-System Programmable CPLD
Internal Timing Parameters
Symbol
Parameter
XC9572-7
Min
Max
2.5
1.5
4.5
5.5
2.5
0.0
3.0
2.0
4.5
0.5
1.5
3.0
0.5
6.5
7.5
2.0
10.0
8.0
4.0
1.0
4.0
10.0
2.5
11.0
9.5
3.5
1.0
4.5
2.5
3.5
0.5
7.0
10.0
3.0
11.5
11.0
3.5
1.0
5.0
XC9572-10
Min
Max
3.5
2.5
6.0
6.0
3.0
0.0
3.0
2.5
3.5
1.0
3.5
4.5
0.5
8.0
XC9572-15
Min
Max
4.5
3.0
7.5
11.0
4.5
0.0
2.5
3.0
5.0
3.0
Units
Buffer Delays
t
IN
Input buffer delay
t
GCK
GCK buffer delay
t
GSR
GSR buffer delay
t
GTS
GTS buffer delay
t
OUT
Output buffer delay
t
EN
Output buffer enable/disable delay
Product Term Control Delays
t
PTCK
Product term clock delay
t
PTSR
Product term set/reset delay
t
PTTS
Product term 3-state delay
Internal Register and Combinatorial delays
t
PDI
Combinatorial logic propagation delay
t
SUI
Register setup time
t
HI
Register hold time
t
COI
Register clock to output valid time
t
AOI
Register async. S/R to output delay
t
RAI
Register async. S/R recovery before clock
t
LOGI
Internal logic delay
t
LOGILP
Internal low power logic delay
Feedback Delays
t
F
FastCONNECT matrix feedback delay
t
LF
Function Block local feeback delay
Time Adders
t
PTA
3
Incremental Product Term Allocator delay
t
SLEW
Slew-rate limited delay
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
3. t
PTA
is multiplied by the span of the function as defined in the family data sheet.
December 4, 1998 (Version 3.0)
5
XILINX [ XILINX, INC ]
