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R
XCR3128XL 128 Macrocell CPLD
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DS016 (v1.8) January 8, 2002
Preliminary Product Specification
Features
Description
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Lowest power 128 macrocell CPLD
The XCR3128XL is a 3.3V 128 macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of eight function blocks provide
3,000 usable gates. Pin-to-pin propagation delays are
6.0 ns with a maximum system frequency of 145 MHz.
6.0 ns pin-to-pin logic delays
System frequencies up to 145 MHz
128 macrocells with 3,000 usable gates
Available in small footprint packages
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144-pin TQFP (108 user I/O pins)
144-ball CS BGA (108 user I/O)
100-pin VQFP (84 user I/O)
TotalCMOS Design Technique for Fast
Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
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Optimized for 3.3V systems
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Ultra low power operation
5V tolerant I/O pins with 3.3V core supply
Advanced 0.35 micron five layer metal EEPROM
process
Fast Zero Power™ (FZP) CMOS design
technology
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Figure 1 and Table 1 showing the I vs. Frequency of our
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XCR3128XL TotalCMOS CPLD (data taken with eight
resetable up/down, 16-bit counters at 3.3V, 25°C).
Advanced system features
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In-system programming
Input registers
Predictable timing model
Up to 23 available clocks per function block
Excellent pin retention during design changes
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Four global clocks
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60
50
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Eight product term control terms per function block
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Fast ISP programming times
30
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10
Port Enable pin for additional I/O
2.7V to 3.6V supply voltage at industrial temperature
range
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Programmable slew rate control per output
Security bit prevents unauthorized access
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Refer to XPLA3 family data sheet (DS012) for
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60
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100 120 140
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architecture description
Frequency (MHz)
DS016_01_112100
Figure 1: Typical I vs. Frequency at V = 3.3V, 25°C
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CC
Table 1: Typical I vs. Frequency at V = 3.3V, 25°C
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Frequency (MHz)
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1
5
10
20
40
60
25.3
80
100
120
49.7
140
Typical I (mA)
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0.5
2.2
4.4
8.7
17.1
33.6
41.6
57.7
CC
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS016 (v1.8) January 8, 2002
www.xilinx.com
1
Preliminary Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
