0
R
XCR3128XL 128 Macrocell CPLD
0
14
DS016 (v1.8) January 8, 2002
Preliminary Product Specification
Features
•
•
•
•
•
Lowest power 128 macrocell CPLD
6.0 ns pin-to-pin logic delays
System frequencies up to 145 MHz
128 macrocells with 3,000 usable gates
Available in small footprint packages
- 144-pin TQFP (108 user I/O pins)
- 144-ball CS BGA (108 user I/O)
- 100-pin VQFP (84 user I/O)
Optimized for 3.3V systems
- Ultra low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM
process
- Fast Zero Power™ (FZP) CMOS design
technology
Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 available clocks per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
Fast ISP programming times
Port Enable pin for additional I/O
2.7V to 3.6V supply voltage at industrial temperature
range
Programmable slew rate control per output
Security bit prevents unauthorized access
Refer to XPLA3 family data sheet (DS012) for
architecture description
Description
The XCR3128XL is a 3.3V 128 macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of eight function blocks provide
3,000 usable gates. Pin-to-pin propagation delays are
6.0 ns with a maximum system frequency of 145 MHz.
TotalCMOS Design Technique for Fast
Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
and
showing the I
CC
vs. Frequency of our
XCR3128XL TotalCMOS CPLD (data taken with eight
resetable up/down, 16-bit counters at 3.3V, 25°C).
70
60
Typical ICC (mA)
50
40
30
20
10
0
0
20
40
60
80
100
Frequency (MHz)
120
140
•
•
•
•
•
•
•
•
DS016_01_112100
Figure 1:
Typical I
CC
vs. Frequency at V
CC
= 3.3V, 25°C
Table 1:
Typical I
CC
vs. Frequency at V
CC
= 3.3V, 25°C
Frequency (MHz)
Typical I
CC
(mA)
0
0
1
0.5
5
2.2
10
4.4
20
8.7
40
17.1
60
25.3
80
33.6
100
41.6
120
49.7
140
57.7
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DS016 (v1.8) January 8, 2002
Preliminary Product Specification
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