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XCS40XL-4PQ208C 参数 Datasheet PDF下载

XCS40XL-4PQ208C图片预览
型号: XCS40XL-4PQ208C
PDF下载: 下载PDF文件 查看货源
内容描述: 斯巴达和Spartan- XL FPGA [Spartan and Spartan-XL FPGA]
分类和应用:
文件页数/大小: 83 页 / 770 K
品牌: XILINX [ XILINX, INC ]
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Spartan and Spartan-XL FPGA
Families Data Sheet
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DS060 (v1.8) June 26, 2008
Product Specification
System level features
- Available in both 5V and 3.3V versions
- On-chip SelectRAM™ memory
- Fully PCI compliant
- Full readback capability for program verification
and internal node observability
- Dedicated high-speed carry logic
- Internal 3-state bus capability
- Eight global low-skew clock or signal networks
- IEEE 1149.1-compatible Boundary Scan logic
- Low cost plastic packages available in all densities
- Footprint compatibility in common packages
Fully supported by powerful Xilinx ISE
®
Classics
development system
- Fully automatic mapping, placement and routing
Introduction
The Spartan
®
and the Spartan-XL FPGA families are a
high-volume production FPGA solution that delivers all the
key requirements for ASIC replacement up to 40,000 gates.
These requirements include high performance, on-chip
RAM, core solutions and prices that, in high volume,
approach and in many cases are equivalent to mask pro-
grammed ASIC devices.
By streamlining the Spartan series feature set, leveraging
advanced process technologies and focusing on total cost
management, the Spartan series delivers the key features
required by ASIC and other high-volume logic users while
avoiding the initial cost, long development cycles and inher-
ent risk of conventional ASICs. The Spartan and Spar-
tan-XL families in the Spartan series have ten members, as
shown in
Table 1.
Additional Spartan-XL Family Features
Spartan/Spartan-XL FPGA Features
Note: The Spartan series devices described in this data
sheet include the 5V Spartan family and the 3.3V
Spartan-XL family. See the
for more
advanced members for the
.
First ASIC replacement FPGA for high-volume
production with on-chip RAM
Density up to 1862 logic cells or 40,000 system gates
Streamlined feature set based on XC4000 architecture
System performance beyond 80 MHz
Broad set of AllianceCORE and LogiCORE™
predefined solutions available
Unlimited reprogrammability
Low cost
Max
System
Gates
5,000
10,000
20,000
30,000
40,000
3.3V supply for low power with 5V tolerant I/Os
Power down input
Higher performance
Faster carry logic
More flexible high-speed clock network
Latch capability in Configurable Logic Blocks
Input fast capture latch
Optional mux or 2-input function generator on outputs
12 mA or 24 mA output drive
5V and 3.3V PCI compliant
Enhanced Boundary Scan
Express Mode configuration
Table 1:
Spartan and Spartan-XL Field Programmable Gate Arrays
Logic
Device
XCS05 and XCS05XL
XCS10 and XCS10XL
XCS20 and XCS20XL
XCS30 and XCS30XL
XCS40 and XCS40XL
Cells
238
466
950
1368
1862
Typical
Gate Range
(Logic and RAM)
(1)
2,000-5,000
3,000-10,000
7,000-20,000
10,000-30,000
13,000-40,000
CLB
Matrix
10 x 10
14 x 14
20 x 20
24 x 24
28 x 28
Total
CLBs
100
196
400
576
784
Max.
Total
No. of
Avail. Distributed
Flip-flops User I/O RAM Bits
360
616
1,120
1,536
2,016
77
112
160
192
205
(2)
3,200
6,272
12,800
18,432
25,088
Notes:
1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
2. XCS40XL provided 224 max I/O in CS280 package discontinued by
© 1998-2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS060 (v1.8) June 26, 2008
Product Specification
1