YGV629 参数 Datasheet PDF下载

YGV629

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Pin Table

Pin Name

No. I/O

CPU Interface

D7-0

8

I/O

PS2-0

3

I

CS_N

1

I

RD_N

1

I

WR_N

1

I

WAIT_N

1

OT

READY_N

1

OT

INT_N

1

Od

SER_N

1

I

SCS_N

1

I

SDIN

1

I

SDOUT

1

OT

SCLK

1

I

RESET_N

1

I

Pattern Memory Interface

MD15-0

16 I/O

MA24-0

25 OT

MOE_N

1

OT

MWE_N

1

OT

RAHZ_N

1

I

Monitor Interface

R,G,B

3

O

IREF

1

-

DR5-0

6

O

DG5-0

6

O

DB5-0

6

O

VSYNC_N

1

O

HCSYNC_N

1

O

I

I

O

O

O

O

I

O

I

I

-

I

Function

CPU Data Bus

CPU Port Selection

Chip Select

Read Pulse

Write Pulse

CPU Bus Wait

CPU Bus Ready

Interrupt

CPU Interface Selection

Serial Interface Chip Select

Serial Interface Data Input

Serial Interface Data Output

Serial Clock Input

Reset

Pattern Memory Data Bus

Pattern Memory Address Bus

Pattern Memory Output Enable

Pattern Memory Write Pulse

Pattern Memory High Impedance Switching

Analog Image Output

DAC Reference Power Supply

Digital Image R Output

Digital Image G Output

Digital Image B Output

Vertical Synchronizing Signal Output

Horizontal Synchronizing / Composite

Synchronizing Signal Output

Vertical Synchronizing Input

Horizontal Synchronizing Input

Display Timing Output

Sub-carrier Clock

YS Output

Dot Clock Output

Reference Clock Input

X’tal connection pin

Display system Clock Input

Display system Clock Selection

PLL Filter Connection

PLL Control

OT: 3-state output, 5Tr: 5V Tolerant,

Level

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

Analog

Analog

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

○

○

4mA

4mA

4mA

4mA

5Tr

○

○

○

○

○

○

○

○

○

○

○

○

○

○

○

○

○

○

○

Drive

4mA

4mA

4mA

4mA

4mA

4mA

4mA

4mA

4mA

4mA

4mA

4mA

4mA

4mA

VSIN_N

1

HSIN_N

1

BLANK_N

1

FSC

1

YS_N

1

DOTCLK

1

Clock

XIN

1

XOUT

1

DTCKIN

1

DTCKS_N

1

FILTER

1

PLLCTL5-0

6

Od: open drain output,

LVCMOS

LVCMOS

Analog

LVCMOS

Drive: driving capability

○

○

○

Note) VC1 has no built-in pull up resistor. Pull up the pins externally as necessary.

The tolerant attribute is an attribute of the input buffer, output buffer that can become the high-impedance

state, and bi-directional buffer, and indicates it can endure the 5V signal.

-

5

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4GV629A50