YMF754
b6................PER: Parity Error Response
This bit enables DS-1E responses to Parity Error.
“0”: DS-1E ignores all parity errors.
(default)
“1”: DS-1E performs error operation when DS-1E detects a parity error.
b8................SER: SERR# Enable
This bit enables DS-1E to drive SERR#.
“0”: Do not drive SERR#.
Error on special cycle.
(default)
“1”: Drives SERR# when DS-1E detects an Address Parity Error on normal target cycle or a Data Parity
06-07h: Status
Read / Write Clear
Default: 0210h
Access Bus Width: 8, 16, 32-bit
b15
DPE
b14
SSE
b13
RMA
b12
RTA
b11
STA
b10
b9
b8
DPD
b7
-
b6
-
b5
-
b4
CAP
b3
-
b2
-
b1
-
b0
-
DEVT
b4................CAP: Capability
(Read Only)
This bit is read only.
When 58-59h :
This bit indicates that DS-1E supports the capability register.
ACPI Mode register, ACPI bit is “0”, the bit is “1”. When ACPI bit is “1”, the bit is “0”.
b8................DPD: Data Parity Error Detected
This bit indicates that DS-1E detects a Data Parity Error during a PCI master cycle.
b[10:9] ........DEVT: DEVSEL Timing
(Read Only)
This bit indicates that the decoding speed of DS-1E is Medium.
b11..............STA: Signaled Target Abort
This bit indicates that DS-1E terminates a transaction with Target Abort during a target cycle.
b12..............RTA: Received Target Abort
This bit indicates that a transaction is terminated with Target Abort while DS-1E is in the master memory
cycle.
b13..............RMA: Received Master Abort
This bit indicates that a transaction is terminated with Master Abort while DS-1E is in the master memory
cycle.
b14..............SSE: Signaled System Error
This bit indicates that DS-1E asserts SERR#.
b15..............DPE: Detected Parity Error
This bit indicates that DS-1E detects Address Parity Error or Data Parity Error during a transaction.
June 28, 1999
-12-
YAMAHA [ YAMAHA CORPORATION ]
