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MT8889CN 参数 Datasheet PDF下载

MT8889CN图片预览
型号: MT8889CN
PDF下载: 下载PDF文件 查看货源
内容描述: 集成双音多频收发器自适应微型接口 [Integrated DTMF Transceiver with Adaptive Micro Interface]
分类和应用: 电信集成电路电信信令电路电信电路光电二极管
文件页数/大小: 31 页 / 494 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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MT8889C
Integrated DTMF Transceiver
with Adaptive Micro Interface
Features
Central office quality DTMF transmitter/
receiver
Low power consumption
High speed adaptive micro interface
Adjustable guard time
Automatic tone burst mode
Call progress tone detection to -30dBm
DS5433
ISSUE 7
March 2001
Ordering Information
MT8889CE
20 Pin Plastic DIP
MT8889CS
20 Pin SOIC
MT8889CN
24 Pin SSOP
-40
°
C to +85
°
C
Applications
Credit card systems
Paging systems
Repeater systems/mobile radio
Interconnect dialers
Personal computers
The receiver section is based upon the industry
standard MT8870 DTMF receiver while the
transmitter utilizes a switched capacitor D/A
converter for low distortion, high accuracy DTMF
signalling. Internal counters provide a burst mode
such that tone bursts can be transmitted with precise
timing. A call progress filter can be selected allowing
a microprocessor to analyze call progress tones.
The MT8889C utilizes an adaptive micro interface,
which allows the device to be connected to a number
of popular microcontrollers with minimal external
logic.
Description
The MT8889C is a monolithic DTMF transceiver with
call progress filter.
It is fabricated in CMOS
technology offering low power consumption and high
reliability.
Functional Description
The MT8889C Integrated DTMF Transceiver consists
of a high performance DTMF receiver with an
internal gain setting amplifier and a DTMF generator,
TONE
D/A
Converters
Row and
Column
Counters
Transmit Data
Register
Status
Register
Data
Bus
Buffer
D0
D1
D2
D3
Tone Burst
Gating Cct.
IN+
IN-
GS
OSC1
OSC2
Oscillator
Circuit
Bias
Circuit
V
DD
V
Ref
V
SS
+
-
Dial
Tone
Filter
Control
Logic
Interrupt
Logic
IRQ/CP
High Group
Filter
Low Group
Filter
Control
Logic
Digital
Algorithm
and Code
Converter
Control
Register
A
Control
Register
B
I/O
Control
DS/RD
CS
R/W/WR
RS0
Steering
Logic
Receive Data
Register
ESt
St/GT
Figure 1 - Functional Block Diagram
1