MT8888C
Pin Description (continued)
Pin #
20
18
24
22
28
26
Name
ESt
Description
Data Sheet
Early Steering
output. Presents a logic high once the digital algorithm has
detected a valid tone pair (signal condition). Any momentary loss of signal
condition will cause ESt to return to a logic low.
Steering Input/Guard Time
output (bidirectional). A voltage greater than V
TSt
detected at St causes the device to register the detected tone pair and update the
output latch. A voltage less than V
TSt
frees the device to accept a new tone pair.
The GT output acts to reset the external steering time-constant; its state is a
function of ESt and the voltage on St.
Positive power supply (5 V typical).
No Connection.
19
23
27
St/GT
20
24
28
V
DD
NC
8, 9, 3,5,10,
16,17 11,16,
23,25
1.0
Functional Description
The MT8888C Integrated DTMF Transceiver consists of a high performance DTMF receiver with an internal gain
setting amplifier and a DTMF generator which employs a burst counter to synthesize precise tone bursts and
pauses. A call progress mode can be selected so that frequencies within the specified passband can be detected.
The Intel micro interface allows microcontrollers, such as the 8080, 80C31/51 and 8085, to access the MT8888C
internal registers.
2.0
Input Configuration
The input arrangement of the MT8888C provides a differential-input operational amplifier as well as a bias source
(V
Ref
), which is used to bias the inputs at V
DD
/2. Provision is made for connection of a feedback resistor to the op-
amp output (GS) for gain adjustment. In a single-ended configuration, the input pins are connected as shown in
Figure 3. Figure 4 shows the necessary connections for a differential input configuration.
3.0
Receiver Section
Separation of the low and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order
switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies
(see Table 1). These filters incorporate notches at 350 Hz and 440 Hz for exceptional dial tone rejection. Each filter
output is followed by a single order switched capacitor filter section, which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of
unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the
incoming DTMF signals.
3
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
