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MT88E39AS 参数 Datasheet PDF下载

MT88E39AS图片预览
型号: MT88E39AS
PDF下载: 下载PDF文件 查看货源
内容描述: 主叫号码Identi网络阳离子电路 [Calling Number Identification Circuit]
分类和应用: 电信电路电话电路光电二极管
文件页数/大小: 16 页 / 258 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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MT88E39
Calling Number Identification Circuit
(CNIC1.1)
Data Sheet
Features
1200 baud Bell 202 and CCITT V.23 Frequency
Shift Keying (FSK) demodulation
Compatible with Bellcore GR-30-CORE, SR-TSV-
002476, TIA/EIA-716 and ETSI 300 778-1
High input sensitivity
Dual mode 3-wire data interface (Serial FSK data
stream or MT88E43 compatible 1 byte buffer)
Internal gain adjustable amplifier
Carrier detect status output
Uses 3.579545 MHz crystal or ceramic resonator
3 to 5 V
±10%
supply voltage
Low power CMOS with power down mode
Direct pin to pin replacement of MT8841 and
MT88E41
Ordering Information
MT88E39AS
MT88E39ASR
MT88E39AS1
MT88E39ASR1
16
16
16
16
Pin
Pin
Pin
Pin
SOIC
SOIC
SOIC*
SOIC*
Tubes
Tape & Reel
Tubes
Tape & Reel
November 2004
*Pb Free Matte Tin
-40°C to +85°C
Description
The MT88E39 Calling Number Identification Circuit
(CNIC1.1) is a CMOS integrated circuit which provides
an interface to calling line information delivery services
that utilize 1200 baud Bell 202 or CCITT V.23 FSK data
transmission schemes. The MT88E39 receives and
demodulates the FSK signal and outputs the data into
a simple dual mode 3-wire serial interface which
eliminates the need for an UART.
The MT88E39 is Bellcore, ETSI and NTT compatible
and can operate in 3 V and 5 V applications. It is a pin
to pin replacement of the MT8841 and MT88E41 by
operating in the MT88E41 FSK interface mode (mode
0) when placed in a MT88E41 socket. New designs
may also choose the MT88E43 compatible interface
(mode 1) where the microcontroller reads the FSK byte
from a 1 byte buffer.
Applications
Global (North America, Japan, Europe) FSK
based CID (Calling Identity Delivery) / CLIP
(Calling Line Identity Presentation)
Feature phones, adjunct boxes
FAX machines
Telephone answering machines
Computer Telephony Integration (CTI)
Battery powered applications
GS
IN-
IN+
-
+
Receive
Bandpass
Filter
FSK
Demodulator
Data and Timing
Recovery
DATA
DR
DCLK
CAP
V
Ref
Bias
Generator
Carrier
Detector
CD
Clock
Generator
to other
circuits
PWDN
OSC1 OSC2
MODE
IC
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1998 - 2004, Zarlink Semiconductor Inc. All Rights Reserved.