MT8941B
Mode
#
M
S
0
M
S
1
M
S
2
M
S
3
Data Sheet
Operating Modes
DPLL #1
NORMAL MODE:
Provides the T1 (1.544 MHz) clock
synchronized to the falling edge of the input
frame pulse (F0i).
NORMAL MODE
NORMAL MODE
NORMAL MODE
DPLL #2
Properly phase related External 4.096 MHz
clock and 8 kHz frame pulse provide the ST-
BUS clock at 2.048 MHz.
NORMAL MODE:
F0b is an input but has no function in this mode.
External 4.096 MHz provides the ST-BUS clock
and Frame Pulse at 2.048 MHz and 8 kHz,
respectively.
NORMAL MODE:
Provides the CEPT/ST-BUS compatible timing
signals locked to the 8 kHz input signal (C8Kb).
Same as mode ‘0’.
SINGLE CLOCK-1 MODE
F0b is an input but has no function in this mode.
Same as mode 2.
SINGLE CLOCK-1 MODE:
Provides the CEPT/ST-BUS compatible timing
signals locked to the 8 kHz internal signal
provided by DPLL #1.
Same as mode ‘0’.
F0b is an input and DPLL #2 locks on to
it only if it is at 16 kHz to provide the ST-BUS
control signals.
Same as mode 2.
FREE-RUN MODE:
Provides the ST-BUS timing signals with no
external inputs except the master clock.
Same as mode ‘0’.
SINGLE CLOCK-2 MODE:
F0b is an input but has no function in this mode.
Same as mode 2.
SINGLE CLOCK-2 MODE:
Provides the CEPT/ST-BUS compatible timing
signals locked to the 8 kHz internal signal
provided by DPLL #1.
0
0
0
0
0
1
2
0
0
0
0
0
1
1
0
3
4
5
6
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
DIVIDE-1 MODE
DIVIDE-1 MODE
DIVIDE-1 MODE
DIVIDE-1 MODE:
Divides the CVb input by 193. The divided
output is connected to DPLL #2.
NORMAL MODE
NORMAL MODE
7
8
9
10
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
NORMAL MODE
NORMAL MODE
DIVIDE-2 MODE
DIVIDE-2 MODE
DIVIDE-2 MODE
DIVIDE-2 MODE:
Divides the CVb input by 256. The divided
output is connected to DPLL#2.
11
12
13
14
1
1
1
1
0
1
1
1
1
0
0
1
1
0
1
0
15
1
1
1
1
Table 4 - Summary of Modes of Operation - DPLL #1 and #2
When MS3 is HIGH, DPLL #2 operates in any of the major modes selected by MS0 and MS1. When MS3 is LOW,
it overrides the major mode selected and DPLL#2 accepts an external clock of 4.096 MHz on C4b (pin 13) to
provide the 2.048 MHz clocks (C2o and C2o) and the 8 kHz frame pulse (F0b) compatible with the ST-BUS format.
The mode select bit MS2 controls the direction of the signal on F0b (pin 6).
When MS2 is LOW, the F0b pin is an 8 kHz frame pulse input. This input is effective only when MS3 is also LOW
and pin C4b is fed by a 4.096 MHz clock, which has a proper phase relationship with the signal on F0b (refer Figure
18). Otherwise, the input on pin F0b will have no bearing on the operation of DPLL #2, unless it is in FREE-RUN
mode as selected by MS0 and MS1. In FREE-RUN mode, the input on F0b is treated the same way as the C8Kb
input is in NORMAL mode. The frequency of the signal on F0b should be 16 kHz for DPLL #2 to lock and generate
the ST-BUS compatible clocks at 4.096 MHz and 2.048 MHz.
8
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
