MT8941BE 参数 Datasheet PDF下载

MT8941B

M

S

2

1

0

M

S

3

1

1

Data Sheet

Functional Description

Provides CEPT/ST-BUS 4.096 MHz and 2.048 MHz clocks and

8kHz frame pulse depending on the major mode selected.

Provides CEPT/ST-BUS 4.096 MHz & 2.048 MHz clocks

depending on the major mode selected while F0b acts as an input.

However, the input on F0b has no effect on the operation of DPLL

#2 unless it is in FREE-RUN mode.

Overrides the major mode selected and accepts properly phase

related external 4.096 MHz clock and 8 kHz frame pulse to provide

the ST-BUS compatible clock at 2.048 MHz.

Overrides the major mode selected and accepts a 4.096 MHz

external clock to provide the ST-BUS clock and frame pulse at

2.048 MHz and 8 kHz, respectively.

Table 3 - Minor Modes of DPLL #2

0

0

1

0

In FREE-RUN mode, DPLL #2 generates the stand-alone CEPT and ST-BUS timing and framing signals with no

external inputs except the master clock set at 16.384 MHz. The DPLL makes no correction in this configuration and

provides the timing signals without any jitter.

The operation of DPLL #2 in SINGLE CLOCK-1 mode is identical to SINGLE CLOCK-2 mode, providing the CEPT

and ST-BUS compatible timing signals synchronized to the internal 8 kHz signal obtained from DPLL#1 in DIVIDE

mode. When SINGLE CLOCK-1 mode is selected for DPLL #2, it automatically selects the DIVIDE-1 mode for

DPLL #1, and thus, an external 1.544 MHz clock signal applied at CVb (pin 21) is divided by DPLL #1 to generate

the internal signal at 8 kHz on to which DPLL #2 locks. Similarly when SINGLE CLOCK-2 mode is selected, DPLL

#1 is in DIVIDE-2 mode, with an external signal of 2.048 MHz providing the internal 8 kHz signal to DPLL #2. In

both these modes, this internal signal is available on C8Kb (pin 10) and DPLL #2 locks to the falling edge to provide

the CEPT and ST-BUS compatible timing signals. This is in contrast to the Normal mode where these timing signals

are synchronized with the falling edge of the 8 kHz signal on C8Kb.

Minor modes of DPLL #2

The minor modes for DPLL #2 depends upon the status of the mode select bits MS2 and MS3 (pins 7 and 17).

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