MT8979
CEPT PCM 30/CRC-4 Frame & Interface
Data Sheet
Features
•
•
•
•
•
•
•
•
•
•
Single chip primary rate 2048 kbit/s CEPT
transceiver with CRC-4 option
Meets CCITT Recommendation G.704
Selectable HDB3 or AMI line code
Tx and Rx frame and multiframe synchronization
signals
Two frame elastic buffer with 32
µsec
jitter buffer
Frame alignment and CRC error counters
Insertion and detection of A, B, C, D signalling
bits with optional debounce
On-chip attenuation ROM with option for ADI
codecs
Per channel, overall and remote loop around
ST-BUS compatible
Ordering Information
MT8979AE
28 Pin PDIP
MT8979AP
44 Pin PLCC
MT8979APR
44 Pin PLCC
MT8979AE1
28 Pin PDIP*
MT8979AP1
44 Pin PLCC*
MT8979APR1 44 Pin PLCC*
*Pb Free Matte Tin
Tubes
Tubes
Tape & Reel
Tubes
Tubes
Tape & Reel
February 2005
ISO-CMOS ST-BUS
TM
Family
-40°C to +85°C
Description
The MT8979 is a single chip CEPT digital trunk
transceiver that meets the requirements of CCITT
Recommendation
G.704
for
digital
multiplex
equipment.
The MT8979 is fabricated in Zarlink’s low power ISO-
CMOS technology.
Applications
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•
•
•
Primary rate ISDN network nodes
Multiplexing equipment
Private network: PBX to PBX links
High speed computer to computer links
TxMF
C2i
F0i
RxMF
DSTi
DSTo
ADI
CSTi0
CSTi1
CSTo
V
DD
ST-BUS
Timing
Circuitry
Digital
Attenuator
ROM
2 Frame
Elastic Buffer
with Slip
Control
CEPT
Link
Interface
RxD
Remote
&
Digital
Loop-
backs
RxA
RxB
TxA
TxB
PCM/Data
Interface
Serial
Control
Interface
ABCD Bit RAM
Phase
Detector
XCtl
XSt
Control Logic
CEPT
Counter
E2i
E8Ko
V
SS
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
