MT8980D
Data Sheet
Bit Cell Boundaries
2.0V
0.8V
C4i
tSIH
2.0V
0.8V
STi0
to
STi7
tSIS
Figure 16 - Serial Inputs
AC Electrical Characteristics† - Processor Bus (Figures 11 and 17)
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Test Conditions
1
2
3
4
Chip Select Setup Time
Read/Write Setup Time
Address Setup Time
tCSS
tRWS
tADS
tAKD
tAKD
tFWS
tSWD
tRDS
tDHT
tDHT
tRDZ
tCSH
tRWH
tADH
tAKH
20
25
25
0
5
ns
ns
ns
ns
5
Acknowledgement Delay Fast
Slow
40
100
7.2
CL=150 pF
2.7
20
cycles C4i cycles1
5
6
7
8
Fast Write Data Setup Time
Slow Write Data Delay
Read Data Setup Time
ns
2.0
1.7
0.5
cycles C4i cycles1
cycles C4i cycles1, CL= 150 pF
Data Hold Time
Read
Write
20
20
ns
ns
ns
ns
ns
ns
ns
RL=1 KΩ∗, CL=150 pF
10
50
9
Read Data To High Impedance
90
RL=1 KΩ∗, CL=150 pF
10 Chip Select Hold Time
11 Read/Write Hold Time
12 Address Hold Time
0
0
0
13 Acknowledgement Hold Time
10
60
80
RL=1 KΩ∗, CL=150 pF
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
1. Processor accesses are dependent on the C4i clock, and so some timings are expressed as multiples of the C4i clock period.
16
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
