MT8981D
Pin Description (continued)
Pin #
40
44
DIP PLCC
Data Sheet
Name
R/W
CS
Description
Read or Write (Input).
This is the input for the read/write signal on the microprocessor interface -
high for read, low for write.
Chip Select (Input).
This is the input for the active low chip select on the microprocessor interface.
20
21
23
24
22-24 25-27 D7-D5
Data 7 to 5 (Three-state I/O Pins).
These are the bidirectional data pins on the microprocessor
interface.
25-29 29-33 D4-D0
Data 4 to 0 (Three-state I/O Pins).
These are the bidirectional data pins on the microprocessor
interface.
30
34
V
SS
IC
Power Input.
Negative Supply (Ground).
Internal Connections.
Leave pins disconnected.
31-34 35-38
35
39
STo3
ST-BUS Output 3 (Three-state Outputs).
These are the pins for the four 2048 kbit/s ST-BUS output
streams.
36-38 41-43 STo2-
ST-BUS Output 2 to 0 (Three-state Outputs).
These are the pins for the four 2048 kbit/s ST-BUS
STo0 output streams.
39
44
ODE
Output Drive Enable (Input).
If this input is held high, the STo0-STo3 output drivers function
normally. If this input is low, the STo0-STo3 output drivers go into their high impedance state.
NB:
Even when ODE is high, channels on the STo0-STo3 outputs can go high impedance under software
control.
IC
Internal Connection.
Leave pin disconnected.
40
1
Functional Description
In recent years, there has been a trend in telephony towards digital switching, particularly in association with
software control. Simultaneously, there has been a trend in system architectures towards distributed processing or
multi-processor systems.
In accordance with these trends, Zarlink has devised the ST-BUS (Serial Telecom Bus). This bus architecture can
be used both in software-controlled digital voice and data switching, and for interprocessor communications. The
uses in switching and in interprocessor communications are completely integrated to allow for a simple general
purpose architecture appropriate for the systems of the future.
The serial streams of the ST-BUS operate continuously at 2048 kbit/s and are arranged in 125
µs
wide frames
which contain 32 8-bit channels. Zarlink manufactures a number of devices which interface to the ST-BUS; a key
device being the MT8981 chip.
The MT8981 can switch data from channels on ST-BUS inputs to channels on ST-BUS outputs, and simultaneously
allows its controlling microprocessor to read channels on ST-BUS inputs or write to channels on ST-BUS outputs
(Message Mode). To the microprocessor, the MT8981 looks like a memory peripheral. The microprocessor can
write to the MT8981 to establish switched connections between input ST-BUS channels and output ST-BUS
channels, or to transmit messages on output ST-BUS channels. By reading from the MT8981, the microprocessor
can receive messages from ST-BUS input channels or check which switched connections have already been
established.
By integrating both switching and interprocessor communications, the MT8981 allows systems to use distributed
processing and to switch voice or data in an ST-BUS architecture.
3
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
