MT89L80
Data Sheet
NC
STi2
STi1
STi0
DTA
CSTo
ODE
STo0
STo1
STo2
NC
STi3
STi4
STi5
STi6
STi7
V
DD
F0i
C4i
A0
A1
A2
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
STo3
STo4
STo5
STo6
STo7
V
SS
D0
D1
D2
D3
D4
V
SS
DTA
STi0
STi1
STi2
NC
STi3
STi4
STi5
STi6
STi7
V
DD
RESET
F0i
C4i
A0
A1
A2
NC
A3
A4
A5
DS
R/W
44 PIN PLCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CSTo
ODE
STo0
STo1
STo2
NC
STo3
STo4
STo5
STo6
STo7
V
SS
V
DD
D0
D1
D2
D3
D4
NC
D5
D6
D7
CS
V
SS
NC
A3
A4
A5
DS
R/W
CS
D7
D6
D5
NC
18
19
20
21
22
23
24
25
26
27
28
6
5
4
3
2
1
44
43
42
41
40
48 PIN SSOP
(JEDEC MO-118, 300mil Wide)
Figure 2 - Pin Connections
Pin Description
Pin #
44
48
PLCC SSOP
2
2
Name
DTA
Description
Data Acknowledgment
(5 V Tolerant Three-state Output). This active low output
indicates that a data bus transfer is complete. A pull-up resistor is required at this
output.
3-5
7-11
12
3-5
7-11
12,36
13
STi0-2 ST-BUS Inputs 0 to 2
(5 V-tolerant Inputs). Serial data input streams. These streams
have data rates of 2.048 Mbit/s with 32 channels.
STi3-7 ST-BUS Inputs 3 to 7
(5 V-tolerant Inputs). Serial data input streams. These streams
may have data rates of 2.048 Mbit/s with 32channels.
V
DD
+3.3 Volt Power Supply.
RESET Device Reset
(5 V-tolerant input). This pin is only available for the 48-pin SSOP
package.This active low input puts the device in its reset state. It clears the internal
counters and registers. All ST-BUS outputs are set to the high impedance state. In
normal operation. The RESET pin must be held low for a minimum of 100nsec to reset
the device. Internal pull-up.
F0i
Frame Pulse
(5 V-tolerant Input). This is the input for the frame synchronization pulse
for the 2048 kbit/s ST-BUS streams. A low on this input causes the internal counter to
reset on the next negative transition of C4i.
13
14
2
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
