MT89L80
Data Sheet
Bit Cell Boundaries
VHM
VLM
C4i
tSIH
VHM
VLM
STi0
to
STi7
tSIS
Figure 13 - Serial Inputs
AC Electrical Characteristics† - Processor Bus (Figures 14)
Characteristics
Sym
Min
Typ‡
Max
Units
Test Conditions
1
2
3
4
Chip Select Setup Time
Read/Write Setup Time
Address Setup Time
tCSS
tRWS
tADS
0
5
5
ns
ns
ns
Acknowledgment Delay
Control Register Read
Control Register Write
Connection Memory Read
Connection Memory Write
Data Memory Read
tAKD
52
120
ns
CL=150 pF
tAKD
tAKD
tAKD
tAKD
tFWS
tSWD
tRDS
tDHT
tDHT
tRDZ
tCSH
tRWH
tADH
tAKH
25
62
65
120
53
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CL=150 pF
CL=150 pF
CL=150 pF
CL=150 pF
30
560
1220
5
6
7
8
Fast Write Data Setup Time
Slow Write Data Delay
Read Data Setup Time
0
122
90
0
10
5
CL= 150 pF
RL=1 KΩ∗, CL=150 pF
Data Hold Time
Read
Write
Read Data To High Impedance
10
50
9
15
0
90
RL=1 KΩ∗, CL=150 pF
10 Chip Select Hold Time
11 Read/Write Hold Time
12 Address Hold Time
0
8
13 Acknowledgment Hold Time
50
80
RL=1 KΩ∗, CL=150 pF
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
13
Zarlink Semiconductor Inc.
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