MT90401
SONET/SDH System Synchronizer
Data Sheet
Features
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Meets requirements of GR-253-CORE for SONET
Stratum 3 and SONET minimum clock
Meets requirements of GR-1244-CORE Stratum 3
Meets requirements of G.813 Option 1 and Option
2 for SDH Equipment Clocks (SEC) with external
jitter attenuator
Provides OC-3/STM-1, DS3, E3, 19.44 MHz,
DS2, E1, T1, 8 kHz and ST-BUS clock outputs
Accepts reference inputs from two independent
sources
Selectable 1.544 MHz, 2.048 MHz, 19.44 MHz or
8kHz input reference frequencies
Holdover accuracy of 0.02 ppm
Adjustable output clock phase supporting master-
slave arrangements
Hardware or microprocessor control (8 bit
microprocessor interface)
3.3 V supply
JTAG boundary scan
Ordering Information
MT90401AB
80 Pin LQFP
MT90401AB1 80 Pin LQFP*
*Pb Free Matte Tin
-40°C to +85°C
Trays
Trays
January 2005
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Applications
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SONET/SDH Add/Drop multiplexers
SONET/SDH uplinks
Integrated access devices
ATM edge switches
Description
The MT90401 is a digital phase locked loop (DPLL)
that is designed to synchronize SDH (Synchronous
Digital Hierarchy) and SONET (Synchronous Optical
Network) networking equipment. The MT90401 is used
to ensure that the timing of outgoing signals remains
within the limits specified by Telcordia, ANSI and the
ITU during normal operation and in the presence of
disturbances on the incoming synchronization signals.
LOCK
VDD
VSS
TCLR
C20i
TCK
TDI
TMS
TRST
TDO
PRI
SEC
Prioor
Secoor
Master Clock
IEEE
1149.1a
TIE
Corrector
Circuit
Selected
Refer-
ence
TIE
Corrector
Enable
Reference
Select
Virtual
Reference
DPLL
Output
Interface
Circuit
State
Select
Input
Impairment
Monitor
Reference
Select
MUX
Reference
Monitor
State
Select
C155P/N
C19o
C1.5o
C2o
C4o
C6o
C8o
C16o
C44/C34
F0o
F8o
F16o
Feedback
Frequency
Select
MUX
RSEL
Control State Machine
RST MS1 MS2 HOLDOVER PCCi FLOCK D0/D7 A0/A6 CS,DS,R/W
FS1
FS2
Figure 1 - Functional Block Diagram
1
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Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
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