MT9045
T1/E1/OC3 System Synchronizer
Data Sheet
Features
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Supports AT&T TR62411 and Bellcore GR-1244-
CORE Stratum 3, Stratum 4 Enhanced and
Stratum 4 timing for DS1 interfaces
Supports ITU-T G.813 Option 1 clocks for 2048
kbit/s interfaces
Supports ITU-T G.812 Type IV clocks for 1,544
kbit/s interfaces and 2,048 kbit/s interfaces
Supports ETSI ETS 300 011, TBR 4, TBR 12 and
TBR 13 timing for E1 interfaces
Selectable 19.44 MHz, 1.544MHz, 2.048MHz or
8kHz input reference signals
Provides C1.5, C2, C4, C6, C8, C16, and C19
(STS-3/OC3 clock divided by 8) output clock
signals
Provides 5 styles of 8 KHz framing pulses
Holdover frequency accuracy of 0.05 PPM
Holdover indication
Attenuates wander from 1.9Hz
Fast lock mode
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Ordering Information
MT9045AN 48 pin SSOP
-40°C to +85°C
Provides Time Interval Error (TIE) correction
Accepts reference inputs from two independent
sources
JTAG Boundary Scan
November 2003
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Applications
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Synchronization and timing control for multitrunk
T1,E1 and STS-3/OC3 systems
ST-BUS clock and frame pulse sources
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OSCi
OSCo
TCLR
LOCK
VDD
VSS
Master Clock
TCK
TDI
TMS
TRST
TDO
PRI
SEC
Prioor
Secoor
IEEE
1149.1a
TIE
Corrector
Circuit
Virtual
Reference
DPLL
Output
Interface
Circuit
Reference
Select
MUX
Reference
Monitor
Selected
Reference
TIE
Corrector
Enable
Reference
Select
State
Select
Input
Impairment
Monitor
State
Select
C19o
C1.5o
C2o
C4o
C6o
C8o
C16o
F0o
F8o
F16o
RSP
TSP
RSEL
Control State Machine
Feedback
Frequency
Select
MUX
MS1 MS2
RST
HOLDOVER PCCi FLOCK
FS1
FS2
Figure 1 - Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
