MT90502
Multi-Channel AAL2 SAR
Preliminary Datasheet
Features
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AAL2 Segmentation Reassembly device
capable of simultaneously processing up to
1023 active CIDs (AAL2 Channel Identifier) and
1023 active VCs (Virtual Circuits).
Support for up to 255 CIDs per VC. Maximum of
1023 CIDs.
Implements AAL2 Common Part Sub-layer
(CPS) functions specified in ITU I.363.2.
Implements AAL2 Service Specific
Convergence Sub-layer (SSCS) functions for
G.711 PCM and G.726 ADPCM voice.
Supports 44-byte PCM or ADPCM packet
profiles specified in AF-VMOA-0145.00.
CPS packet payload can support up to
64-bytes.
Supports over-subscription of 10:1.
H.100/H.110 compatible TDM bus for PCM or
ADPCM data. Supports both master and slave
TDM bus clock operation.
TDM bus also supports compressed voice such
as ITU G.723, G.728 and G.729 through HDLC
encapsulation.
Three UTOPIA Level 1 ports configurable as
Memory Bank A
SSRAM
(max: 1M x18)
SDRAM
(max: 8M x16)
DS5420
ISSUE 1
November 2001
Ordering Information
MT90502AG
456 Pin Plastic BGA
0 to +70°C
PHY or ATM allowing for connection to an
external AAL5 SAR processor, or for chaining
multiple MT90502 devices. Ports A & B are
configurable as a single 8-bit UTOPIA Level 2
PHY port with 5 ADDR lines.
UTOPIA module provides a cell switching
function with a header translation.
Performs silence suppression for PCM and
ADPCM.
Comfort noise generation.
Capability to inject and recover CPS packets
through the CPU host processor bus.
8-bit or 16-bit microprocessor port, configurable
to Motorola or Intel timing.
Single rail 3.3 V, 456 PBGA.
IEEE 1149 (JTAG) interface.
Memory Bank B (Optional)
SSRAM
(max: 1M x18)
SDRAM
(max: 8M x16)
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MT90502
Dual Memory Controller
UTOPIA
Module
RX
CPS Packets
AAL2 SAR
Receiver
Port
A
RxA Port
TxA Port
TDM Bus
4096 x 64 kbps
TDM
Module
Port
B
Clock and
Frame
Pulse
TX
CPS Packets
AAL2 SAR
Transmitter
Port
C
RxB Port
TxB Port
RxC Port
TxC Port
Clock
Recovery
and
Generation
CPU Interface
JTAG Interface
Figure 1 - MT90502 Functional Block
1
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
