MT90503
2048VC AAL1 SAR
Data Sheet
Features
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AAL1 Segmentation and Reassembly device
capable of simultaneously processing up to 2048
bidirectional VCs
AAL1 cell format for "Structured DS1/E1 N x
64kbps Service" as per ATM Forum AF-VTOA-
0078.000 "Circuit Emulation Services
Interoperability Specifications" (Nx64 Basic
Service, DS1 Nx64 Service with CAS, and E1
Nx64 Service with CAS)
Two UTOPIA ports (Level 2, 16-bit, 50 MHz) with
loopback function for dual fibre ring applications
Third UTOPIA port for connection to an external
AAL5 SAR processor, or for chaining multiple
MT90503 or other SAR or IMA devices
Flexible aggregation capabilities (Nx64) to allow
any combination of 64 Kbps
TDM bus provides 32 bidirectional serial TDM
streams at 2.048, 4.096, or 8.192 Mbps for up to
4096 TDM 64 Kbps channels
Compatible with H.100 and H.110 interfaces
Ordering Information
MT90503AG
503 Pin PBGA
December 2004
•
For temperature range, see page 207.
•
•
TDM to ATM transmission latency less than 250
µs
Support for clock recovery - Adaptive Clock
Recovery, Synchronous Residual Time Stamp
(SRTS) or external
Support master and slave TDM bus clock
operation
8- or 16-bit microprocessor port, configurable to
Motorola or Intel timing
Master clock rate up to 80 MHz
Single power supply device (3.3V)
IEEE 1149 (JTAG) interface
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Control Memory
(external SSRAM)
Address bus and 8- or
16-bit Data bus
Control Memory
Controller
CPU Module
Registers
H.100/
H.110
TDM Bus
4096 x
64kbps
TX_SAR
Module
RX_SAR
Module
UTOPIA
Module
Port
A
Port
B
RXA Port
TXA Port
RXB Port
TXB Port
RXC Port
TXC Port
TDM
Module
Data Memory
Controller
Clock
Recovery
Submodule
Port
C
Boundary
Scan Logic
JTAG
Interface
Clock Signals
Data Memory
(external SSRAM)
Figure 1 - Functionl Block Diagram
1
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Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.
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