MT9074
T1/E1/J1 Single Chip Transceiver
Data Sheet
Features
•
Combined E1 (PCM30) and T1 (D4/ESF) framer,
Line Interface Unit (LIU) and link controller with
optional digital framer only mode
In T1 mode the LIU can recover signals
attenuated by up to 30 dB (5000 ft. of 24 AWG
cable)
In E1 mode the LIU can recover signals
attenuated by up to 30 dB (1900 m. of 0.65 mm
cable)
Two HDLCs: FDL and channel 24 in T1 mode,
timeslot 0 (Sa bits) and timeslot 16 in E1 mode
Two-frame elastic buffer in Rx & Tx (T1)
directions
Programmable transmit delay through transmit
slip buffer
Low jitter DPLL for clock generation
Enhanced alarms, performance monitoring and
error insertion functions
Intel or Motorola non-multiplexed parallel
microprocessor interface
ST-BUS 2.048 Mbit/s backplane bus for both data
and signaling
Japan Telecom J1 Framing and Yellow Alarm
TxDL TxDLCLK
TxMF
August 2005
Ordering Information
MT9074AL
MT9074AP
MT9074APR
MT9074AL1
MT9074AP1
MT9074APR1
100 Pin MQFP
68 Pin PLCC
68 Pin PLCC
100 Pin MQFP*
68 Pin PLCC*
68 Pin PLCC*
*Pb Free Matte Tin
-40°C to +85°C
Trays
Tubes
Tape & Reel
Trays
Tubes
Tape & Reel
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•
•
•
•
•
•
•
•
•
•
•
Hardware data link access
JTAG Boundary Scan
Applications
•
•
•
•
*
E1/T1 add/drop multiplexers and channel banks
CO and PBX equipment interfaces
Primary Rate ISDN nodes
Digital Cross-connect Systems (DCS)
MT9074A was revised after its market introduction. Software can
confirm that the installed chip is the most recent revision of MT9074A
as follows:
1.
In T1 mode, the LSB (Least Significant Bit) of the
Synchronization Status Word - bit 0, Page 3 Address 10H is set
high.
Batch codes 61755.0 or higher, and/or date code beginning with
00, 01, 02, etc.
TxAO TxB TxA
2.
DSTi
CSTi
Tdi
Tdo
Tms
Tclk
Trst
ST-BUS
Interface
IEEE
1149.1
Transmit Framing, Error,
Test Signal Generation and Slip Buffer
Pulse
Generator
Line
Driver
TTIP
TRING
RM
Loop
National
Bit Buffer
Data Link,
HDLC0
HDLC1
Jitter Attenuator
& Clock Control
CAS
Buffer
MT
Loop
ST Loop
PL Loop
CS
DS/RD
DSTo
CSTo
Clock,Data
Recovery
R/W/WR
Rx Equalizer
& Data Slicer
D7~D0
AC4
AC0
Microprocessor
Interface
IRQ
S/FR
BS/LS
OSC1
OSC2
DG Loop
RTIP
RRING
ST-BUS
Interface
Receive Framing, Performance Monitoring,
Alarm Detection, 2 Frame Slip Buffer
RxDLCLK RxDL
RxMF
LOS
RxFP
E1.5o F0b C4b
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2002-2005, Zarlink Semiconductor Inc. All Rights Reserved.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
