CMOS ST-BUS
TM
Family
MT90820
Large Digital Switch
Data Sheet
Features
•
•
•
•
•
•
•
•
•
•
•
2,048
×
2,048 channel non-blocking switching at
8.192 Mb/s
Per-channel variable or constant throughput
delay
Automatic identification of ST-BUS/GCI interfaces
Accept ST-BUS streams of 2.048 Mb/s,
4.096 Mb/s or 8.192 Mb/s
Automatic frame offset delay measurement
Per-stream frame delay offset programming
Per-channel high impedance output control
Per-channel message mode
Control interface compatible to Motorola non-
mulitplexed CPUs
Connection memory block programming
IEEE-1149.1 (JTAG) Test Port
Ordering Information
MT90820AP
84 Pin PLCC
MT90820AL
100 Pin MQFP
MT90820APR
84 Pin PLCC
MT90820AL1
100 Pin MQFP*
MT90820AP1
84 Pin PLCC*
MT90820APR1 84 Pin PLCC*
*Pb Free Matte Tin
Tubes
Trays
Tape & Reel
Trays
Tubes
Tape & Reel
August 2005
-40°C to +85°C
Applications
•
•
•
•
•
•
Medium and large switching platforms
CTI application
Voice/data multiplexer
Digital cross connects
ST-BUS/GCI interface functions
Support IEEE 802.9a standard
V
DD
V
SS
TMS
TDI
TDO
TCK
TRST
IC
RESET
ODE
Test Port
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STi8
STi9
STi10
STi11
STi12
STi13
STi14
STi15
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
STo8
STo9
STo10
STo11
STo12
STo13
STo14
STo15
Serial
to
Parallel
Converter
Loopback
Parallel
Multiple Buffer
Data Memory
Output
MUX
to
Serial
Converter
Internal
Registers
Connection
Memory
Timing
Unit
Microprocessor Interface
CLK
F0i
FE/ WFPS
HCLK
AS/ IM DS/ CS
ALE
RD
R/W
/WR
A7-A0 DTA D15-D8/ CSTo
AD7-AD0
Figure 1 - Functional Block Diagram
1
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Copyright 2000-2005, Zarlink Semiconductor Inc. All Rights Reserved.
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