MT90840
Distributed Hyperchannel Switch
Data Sheet
Features
•
Time slot interchange function between eight
pairs of ST-BUS/GCI/MVIP™ streams (512
channels) and parallel data port
Programmable data rates on the parallel port
(19.44, 16.384, or 6.480 Mbyte/s)
Programmable data rates on the serial port (2.048
Mbps, 4.096 Mbps or 8.192 Mbps)
Supports star and point-to-point connections, and
unidirectional or bidirectional ring topologies for
distributed systems
Input-to-output bypass function on the parallel
data port for use in add/drop applications
Provides elastic buffer at parallel input port in the
receive direction
Provides byte switching for up to 2430 channels
Per-channel direction control on the serial port
side
Per-channel message mode and high-impedance
control on both parallel and serial port sides
8-bit multiplexed microprocessor port compatible
with Intel and Motorola microcontrollers
Guarantees frame integrity when switching nX64
wideband channels such as ISDN H0 channel
Provides external control lines allowing fast
parallel interface to be shared with other devices
ISSUE 3
July 2002
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Ordering Information
MT90840AL
100 Pin PQFP
MT90840AP 84 Pin PLCC
-40°C to 85°C
•
•
Diagnostic alarm functions and clock
phase-status word for clock monitoring
IEEE 1149 (JTAG) boundary scan port
•
•
•
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Applications
•
Bridging ST-BUS/MVIP buses to high speed
Time Division Multiplexed backplanes at
SONET rates (STS-1, STS-3)
High speed isochronous backbones for
distributed PBX and LAN systems
Switch platforms of up to 2430 channels with
guaranteed frame integrity for wideband
channels
Serial bus control and monitoring
Data multiplexing
High speed communications interface
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PDo0
PDo7
CTo0-3
PDi0
PDi7
8
Output
Mux &
Drivers
4
Multiple Pages of 512 Position
TX Path Data Memory
16
2430 Position
TX Path
Connection Memory
8
8
Serial
to
Parallel
&
Bidirectional
I/O
Driver
STi0
STi7
8
8
Parallel
to
Serial
Conver-
ters
Multiple Pages of 2430-Byte
RX Path Data Memory
15
Bidirectional
I/O
Driver
STo0
STo7
PCKR
PCKT
RES
PPFRi
PPFTi/o
F0i/o
Timing
Control
Unit
512 Position
RX Path
Connection Memory
JTAG
5
TEST
Pins
CPU Interface
Internal
Registers
8
8
VSS
R/W\WR
SPCKo
C4/8R1
C4/8R2
AD0-7
DS/RD
Figure 1 - Functional Block Diagram
AS/ALE
DTA
VDD
IRQ
CS
2-231
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
