MT90880/1/2/3
TDM to Packet Processors
Data Sheet
Features
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WAN interface, consisting of 32 input and output
streams at 2.048 or 8.192 Mbs
Up to 1024 bi-directional 64 Kbs channels
N * 64 Kbs trunking of channels across any
stream and channel
1 K by 1 K non-blocking TDM switch
Local TDM interface, with 32 streams at 2.048,
4.096 and 8.192 Mbs
Flexible, multi-protocol packet encapsulation
Dual 100 Mbs MII interfaces for redundancy or for
load balancing
Quality of service features, including weighted fair
queuing, strict priority and queue size limit
thresholds
High performance 33 MHz / 66 MHz 32 bit PCI
bus
Integral Stratum 4E PLL for synchronisation to the
TDM domain
Power consumption of less than 0.75 W
Ordering Information
MT90880B/IG/BP1N
MT90881A/IG/BP1N
MT90882B/IG/BP1N
MT90883A/IG/BP1N
456 ball PBGA
456 ball PBGA
456 ball PBGA
456 ball PBGA
December 2004
-40°C to +85°C
Applications
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Packet backplane interconnection
Circuit Emulation over packet domain
Internet Off-load
Remote Access Concentrators
H.100/H.110 extension and expansion
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Host Control/Data Interface
32 bit, 33MHz / 66MHz 32 PCI
WAN Access
Interface
32 ST-Bus TDM ports
(1024 bi-directional channels)
Administration
PCI Interface
Packet Switch
Fabric Interface
Dual Redundant 100 Mbit/s
MII Interfaces
1Kx1K TDM
Switch
Packetizing
and Circuit
Emulation
Dual Packet
Interface
MAC
TDM Re-
Formatter
Memory Manager
Local TDM Interface
Packet Memory
e.g. for connection to local resource pool 0.125 - 8 MBytes SSRAM
Figure 1 - MT90880 High Level Overview
1
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Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.