ISO
2
-CMOS
MT9162
5 Volt Single Rail Codec
Data Sheet
Features
•
•
•
•
•
•
•
•
•
•
Single 5 volt supply
Programmable
µ−law/A-law
Codec and filters
Fully differential output driver
SSI digital interface
SSI speed control via external pins CSLO-CSL2
Individual transmit and receive mute controls
0 dB gain in receive path
6 dB gain in transmit path
Low power operation
ITU-T G.714 compliant
Ordering Information
MT9162AE
20 Pin PDIP
MT9162AS
20 Pin SOIC
MT9162AN
20 Pin SSOP
MT9162AN1 20 Pin SSOP*
*Pb Free Matte Tin
-40°C to +85°C
Tubes
Tubes
Tubes
Tubes
May 2006
Description
The MT9162 5 V single rail Codec incorporates a built-
in Filter/Codec, transmit anti-alias filter, a reference
voltage and bias source. The device supports both A-
law and
µ-law
requirements.
The analog interface is capable of driving a 20 k ohm
load.
The MT9162 is fabricated in Zarlink's ISO
2
-CMOS
technology ensuring low power consumption and high
reliability.
Applications
•
•
•
Cellular radio sets
Local area communications stations
Line cards
FILTER/CODEC GAIN
VDD
VSS
VBias
VRef
ENCODER
DECODER
6dB
0 dB
Analog
Interface
AIN+
AIN-
AOUT +
AOUT -
Din
Dout
STB
CLOCKin
PCM
Serial
Interface
Timing
Control
PWRST
IC
A/µ
CSL0
CSL1
CSL2 RXMute TXMute
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1999-2006, Zarlink Semiconductor Inc. All Rights Reserved.