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MT9162AS 参数 Datasheet PDF下载

MT9162AS图片预览
型号: MT9162AS
PDF下载: 下载PDF文件 查看货源
内容描述: 5伏单轨编解码器 [5 Volt Single Rail Codec]
分类和应用: 解码器编解码器电信集成电路电信电路光电二极管
文件页数/大小: 22 页 / 569 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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MT9162
AC Characteristics
for A/D (Transmit) Path
- 0dBm0 = A
Lo3.17
- 3.17dB = 1.773V
rms
for
µ-Law
and
- 3.14dB = 1.843V
rms
for A-Law, at the Codec. (V
Ref
=0.6 volts and V
Bias
=2.5 volts.)
Data Sheet
0dBm0 = A
Lo3.14
Characteristics
1
Analog input equivalent to overload
decision
Absolute half-channel gain
AIN
±
to Dout
3
Gain tracking vs. input level
ITU-T G.714 Method 2
Signal to total Distortion vs. input
level.
ITU-T G.714 Method 2
Transmit Idle Channel Noise
Gain relative to gain at
<50Hz
60Hz
200Hz
300 - 3000 Hz
3000 - 3400 Hz
4000 Hz
>4600 Hz
Absolute Delay
Group Delay relative to D
AX
Sym.
A
Li3.17
A
Li3.14
Min.
Typ.
7.334
7.6
Max.
Units
Vp-p
Vp-p
Test Conditions
µ-Law
A-Law
Both at Codec
Transmit filter gain=0dB
setting.
@1020Hz
3 to -40 dBm0
-40 to -50 dBm0
-50 to -55 dBm0
0 to -30 dBm0
-40 dBm0
-45 dBm0
µ-Law
A-Law
2
G
AX1
G
TX
5.2
-0.3
-0.6
-1.6
35
29
24
6.0
6.8
0.3
0.6
1.6
dB
dB
dB
dB
dB
dB
dB
4
D
QX
5
6
N
CX
N
PX
G
RX
8.5
-71
12
-69
-25
-30
0.0
0.25
0.25
-12.5
-25
dBrnC0
dBm0p
dB
dB
dB
dB
dB
dB
dB
µs
µs
µs
µs
µs
-45
-0.25
-0.9
-23
-40
D
AX
D
DX
360
750
380
130
750
7
8
at frequency of minimum
delay
500-600 Hz
600 - 1000 Hz
1000 - 2600 Hz
2600 - 2800 Hz
±100mV
peak signal on
V
DD
µ-law
PSSR1-3 not production
tested
9
Power Supply Rejection
f=1020 Hz
f=0.3 to 3 kHz
f=3 to 4 kHz
f=4 to 50 kHz
PSSR
PSSR1
PSSR2
PSSR3
37
37
40
35
40
dB
dB
dB
dB
† AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
9
Zarlink Semiconductor Inc.