ISO
2
-CMOS ST-BUS FAMILY MT9171/72
Digital Subscriber Interface Circuit
Digital Network Interface Circuit
Data Sheet
Features
•
•
•
•
•
•
•
•
•
Full duplex transmission over a single twisted pair
Selectable 80 or 160 kbit/s line rate
Adaptive echo cancellation
Up to 3 km (9171) and 4 km (9172)
ISDN compatible (2B+D) data format
Transparent modem capability
Frame synchronization and clock extraction
Zarlink ST-BUS compatible
Low power (typically 50 mW), single 5 V supply
Ordering Information
MT9171/72AE
22 Pin PDIP
MT9171/72AN
24 Pin SSOP
MT9171/72AP
28 Pin PLCC
MT9171/72APR
28 Pin PLCC
MT9171/72ANR
24 Pin SSOP
MT9171/72AE1
22 Pin PDIP*
MT9171/72AP1
28 Pin PLCC*
MT9171/72AN1
24 Pin SSOP*
MT9171/72APR1 28 Pin PLCC*
MT9171/72ANR1 24 Pin SSOP*
*Pb Free Matte Tin
-40°C to +85°C
March 2006
Tubes
Tubes
Tubes
Tape &
Tape &
Tubes
Tubes
Tubes
Tape &
Tape &
Reel
Reel
Reel
Reel
Applications
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•
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Digital subscriber lines
High speed data transmission over twisted wires
Digital PABX line cards and telephone sets
80 or 160 kbit/s single chip modem
Description
The MT9171 (DSIC) and MT9172 (DNIC) are pin for
pin compatible replacements for the MT8971 and
MT8972, respectively. They are multi-function devices
capable of providing high speed, full duplex digital
transmission up to 160 kbit/s over a twisted wire pair.
They use adaptive echo-cancelling techniques and
transfer data in (2B+D) format compatible to the ISDN
basic rate. Several modes of operation allow an easy
interface to digital telecommunication networks
including use as a high speed limited distance modem
DSTi/Di
CDSTi/
CDi
Transmit
Interface
Prescrambler
Scrambler
Differentially
Encoded Biphase
Transmitter
Transmit
Filter &
Line Driver
L
OUT
F0/CLD
C4/TCK
F0o/RCK
MS0
MS1
MS2
RegC
Control
Register
Transmit
Timing
Master Clock
Phase Locked
V
Bias
Address
Echo Canceller
Error
Signal
Echo Estimate
—
DPLL
MUX
L
OUT
DIS
Precan
Transmit/
Clock
Receive
Timing &
Control
Sync Detect
Status
Receive
∑
+
Receive
Filter
-1
+2
L
IN
OSC2
DSTo/Do
CDSTo/
CDo
Receive
Interface
De-
Prescrambler
Descrambler
Differentially
Encoded Biphase
Receiver
OSC1
V
DD
V
SS
V
Bias
V
Ref
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1999-2006, Zarlink Semiconductor Inc. All Rights Reserved.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
