MT9171/72
Data Sheet
bit 0
Reg Sel-1
bit 1
Reg Sel-2
bit 2
Loopback
bit 3
bit 4
FUN
bit 5
PSWAP
bit 6
DLO
bit 7
Not Used
Default Mode Selection
(Refer to Table 4a)
Bit
4
5
Name
FUN
1
PSWAP
1
Description
Force Unsync. When set to ’1’, the DNIC is forced out-of-sync to test the SYNC
recovery circuitry. When set to ’0’, the operation continues in synchronization.
Polynomial Swap. When set to ’1’, the scrambling and descrambling polynomials
are interchanged (use for MAS mode only). When set to ’0’, the polynomials retain
their normal designations.
Disable Line Out. When set to ’1’, the signal on L
OUT
is set to V
Bias
. When set to ’0’,
L
OUT
pin functions normally.
Must be set to ’0’ for normal operation.
Table 5 - Diagnostic Register
6
7
DLO
1
Not Used
Notes:
1. When bits 4-7 of the Diagnostic Register are all set to one, the DNIC operates in one of the default modes as defined in Table 4a,
depending upon the status of bit-3.
2. Do not use L
OUT
to L
IN
loopback in DN/SLV mode.
3. Do not use DSTo to DSTi loopback in MOD/MAS mode.
The Diagnostics Register Reset bit (bit 2) of the Control Register determines the reset state of the Diagnostics
Register. If, on writing to the Control Register, this bit is set to logic “0”, the Diagnostics Register will be reset
coincident with the frame pulse. When this bit is logic “1”, the Diagnostics Register will not be reset. In order to use
the diagnostic features, the Diagnostics Register must be continuously written to. The output C-channel sends
status information from the Status Register to the system along with the received HK bit as shown in Table 6.
0
1
2
3
4
5
6
7
SYNC
CHQual
Rx HK
Future Functionality
ID
Status
Register
0
1-2
3
4-6
7
Name
SYNC
CHQual
Rx HK
Future
ID
Function
Synchronization
- When set this bit indicates that synchronization to the received
line data sync pattern has been acquired. For DN mode only.
Channel Quality -
These bits provide an estimate of the receiver’s margin against
noise. The farther this 2 bit value is from 0 the better the SNR.
Housekeeping -
This bit is the received housekeeping (HK) bit from the far end.
Future Functionality.
These bits return Logic 1 when read.
This bit provides a hardware identifier for the DNIC revision. The MT9171/72 will
return a logic “0” for this bit. (Logic “1” returned for MT8972A.)
Table 6 - Status Register
13
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
