ISO
2
-CMOS ST-BUS
FAMILY
MT9171/72
Digital Subscriber Interface Circuit
Digital Network Interface Circuit
Features
•
•
•
•
•
•
•
•
•
Full duplex transmission over a single twisted
pair
Selectable 80 or 160 kbit/s line rate
Adaptive echo cancellation
Up to 3km (9171) and 4 km (9172)
ISDN compatible (2B+D) data format
Transparent modem capability
Frame synchronization and clock extraction
Zarlink ST-BUS compatible
Low power (typically 50 mW), single 5V supply
DS5130
ISSUE 3
February 1999
Ordering Information
MT9171AE
22 Pin Plastic DIP (400 mil)
MT9171AN
24 Pin SSOP
MT9171AP
28 Pin PLCC
MT9172AE
22 Pin Plastic DIP (400 mil)
MT9172AN
24 Pin SSOP
MT9172AP
28 Pin PLCC
-40
°
C to
+
85
°
C
Description
The MT9171 (DSIC) and MT9172 (DNIC) are pin for
pin compatible replacements for the MT8971 and
MT8972, respectively. They are multi-function
devices capable of providing high speed, full duplex
digital transmission up to 160 kbit/s over a twisted
wire pair.
They use adaptive echo-cancelling
techniques and transfer data in (2B+D) format
compatible to the ISDN basic rate. Several modes of
operation allow an easy interface to digital
telecommunication networks including use as a high
speed limited distance modem with data rates up to
160 kbit/s. Both devices function identically but with
the DSIC having a shorter maximum loop reach
specification. The generic "DNIC" will be used to
reference both devices unless otherwise noted.
The MT9171/72 is fabricated in Zarlink’s ISO
2
-
CMOS process.
Applications
•
•
•
•
Digital subscriber lines
High speed data transmission over twisted
wires
Digital PABX line cards and telephone sets
80 or 160 kbit/s single chip modem
DSTi/Di
CDSTi/
CDi
Transmit
Interface
Prescrambler
Scrambler
Differentially
Encoded Biphase
Transmitter
Transmit
Filter &
Line Driver
L
OUT
F0/CLD
C4/TCK
F0o/RCK
MS0
MS1
MS2
RegC
Control
Register
Transmit
Timing
V
Bias
Address
Echo Canceller
Error
Signal
Echo Estimate
—
DPLL
MUX
L
OUT
DIS
Master Clock
Phase Locked
Transmit/
Clock
Receive
Timing &
Control
Sync Detect
Status
Receive
Precan
∑
+
Receive
Filter
-1
+2
L
IN
OSC2
DSTo/Do
CDSTo/
CDo
Receive
Interface
De-
Prescrambler
Descrambler
Differentially
Encoded Biphase
Receiver
OSC1
V
DD
V
SS
V
Bias
V
Ref
Figure 1 - Functional Block Diagram
9-115
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
