ISO
2
-CMOS ST-BUS
TM
Family
MT9173/74
Digital Subscriber Interface Circuit with RxSB
Digital Network Interface Circuit with RxSB
Data Sheet
Features
•
•
•
•
•
•
•
•
•
•
Receive sync output pulse
Full duplex transmission over a single twisted pair
Selectable 80 or 160 kbit/s line rate
Adaptive echo cancellation
Up to 3 km (9173) and 4 km (9174) loop reach
ISDN compatible (2B+D) data format
Transparent modem capability
Frame synchronization and clock extraction
Zarlink ST-BUS compatible
Low power (typically 50 mW), single 5 V supply
MT9173AE
MT9173AN
MT9173AP
MT9173AE1
MT9173AP1
MT9173AN1
MT9174AE
MT9174AN
MT9174AP
December 2005
Ordering Information
24 Pin PDIP
24 Pin SSOP
28 Pin PLCC
24 Pin PDIP*
28 Pin PLCC*
24 Pin SSOP*
24 Pin PDIP
24 Pin SSOP
28 Pin PLCC
*Pb Free Matte Tin
Tubes
Tubes
Tubes
Tubes
Tubes
Tape & Reel
Tubes
Tubes
Tubes
-40°C to +85°C
Description
The MT9173 (DSIC) and MT9174 (DNIC) are
functionally identical to the MT9171/72 except for the
addition of one feature. The MT9173/74 include a
digital output pin indicating the temporal position of the
received "SYNC" bit of the biphase transmission. This
feature is especially useful for systems such as PCS
wireless base station applications requiring close
synchronization between microcells.
The MT9173 and MT9174 are identical except for the
MT9173 having a shorter loop reach. The generic
"DNIC" will be used to reference both devices unless
otherwise noted. The MT9173/74 are fabricated in
Zarlink’s ISO
2
-CMOS process.
Applications
•
•
•
•
•
T
DD
Digital PCS (DECT, CT2, PHS) base stations
requiring cell synchronization
Digital subscriber lines
High speed data transmission over twisted wires
Digital PABX line cards and telephone sets
80 or 160 kbit/s single chip modem
DSTi/Di
CDSTi/
CDi
Transmit
Interface
Prescrambler
Scrambler
Differentially
Encoded Biphase
Transmitter
Transmit
Filter &
Line Driver
L
OUT
F0/CLD
C4/TCK
MS0
MS1
MS2
RegC
Control
Register
Transmit
Timing
Master Clock
Phase Locked
Transmit/
Clock
Receive
Timing &
Control
Sync Detect
Status
Receive
Address
Echo Canceller
Error
Signal
Echo Estimate
—
DPLL
V
Bias
MUX
L
OUT
DIS
Precan
∑
+
Receive
Filter
-1
+2
L
IN
OSC2
DSTo/Do
CDSTo/
CDo
RxSB
Receive
Interface
De-
Prescrambler
Descrambler
Differentially
Encoded Biphase
Receiver
OSC1
V
DD
V
SS
V
Bias
V
Ref
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1999-2005, Zarlink Semiconductor Inc. All Rights Reserved.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
