NJ88C50
Dual Low Power Frequency Synthesiser
DS3805
ISSUE 1.8
June 2002
The NJ88C50 is a low power integrated circuit, designed
as the heart of a fast locking PLL subsystem in a mobile radio
application. It is manufactured on Mitel Semiconductor 1.4
micron double polysilicon CMOS process, which ensures that
low power and low noise performance is achieved. The device
contains two synthesisers, one for the generation of VHF
signals up to 125MHz and a second for UHF (when used with
a mulitmodulus prescaler such as the SP8713/14/15). The
main synthesiser has the capability of driving a dual speed
loop filter and also can perform Fractional-N interpolation.
Both synthesisers use current source outputs from their
phase detectors to minimise external components. Various
sections may be powered down for battery economy.
Ordering Information
NJ88C50/MA/NP - (Industrial temp
range in SSOP package)
AVDD
FIM
FIMB
1
2
3
4
5
6
7
8
9
10
20
19
18
17
AGND
MOD2
MOD1
SCREEN
RSC
RSM
VDD
PDP
GND
PDI
FEATURES
•
•
•
•
•
•
•
30MHz main synthesiser
125MHz auxiliary synthesiser
Programmable output current
from phase detector - up to 10mA
High input sensitivity
Fractional-N interpolator
Supports up to 4 modulus prescalers
SSOP package
DATA
CKIN
STROBE
RI
FIA
RSA
PDA
NJ88C50
16
15
14
13
12
11
APPLICATIONS
•
•
•
•
•
NMT, AMPS, ETACS cellular
GSM, IS-54, RCR-27 cellular
DCS1800 microcellular
DLMR, DSRR, TETRA
DECT, PHP cordless telephones
Figure 1 - Pin assignment
NP20
ABSOLUTE MAXIMUM RATINGS
Storage temperature
Operating temperature
Supply voltage
Voltage on any pin
MOD1
MOD2
RSC
RSM
-55°C to +150°C
-40°C to +85°C
-0.5 to 7.0V
-0.3V to (V
DD
+ 0.3V)
FIM
FIMB
MAIN N
BUFFER
MAIN N-DIVIDER
LATCH
PHASE
DETECTOR
CURRENT
SOURCE
PDI
PDP
DATA
CKIN
STROBE
SERIAL
INPUT
REGISTER
LATCH
LATCH
QBAR
FRACTIONAL-N
SYSTEM
RI
R BUFFER
R DIVIDER
Q
LATCH
FIA
AUX. N
BUFFER
AUX. N-DIVIDER
PHASE
DETECTOR
CURRENT
SOURCE
PDA
RSA
Figure 2 - Simplified block diagram
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
