PDSP16515A
PDSP16515A
Stand Alone FFT Processor
Advance Information
DS3922
ISSUE 2.0
April 1999
Features
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Ordering Information
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Completely self contained FFT Processor
Pin and functionally compatible with the
PDSP16510A
Expanded width internal RAM supports up to 1024
complex points
18 bit internal data bus with block floating point
arithmetic for increased dynamic range
500 MIP operation gives 87 microsecond
transformation times for 1024 points
Up to 45MHz sampling rates with multiple devices.
Up to 85dB noise rejection
A choice of internal window operators with no
external ROM provide up to 67dB side lobe
attenuation.
84 pin PGA or 132 pin surface mount package
Associated Products
PDSP16330
PDSP16256
PDSP16350
PDSP16510A
Pythagoras Processor.
Programmable FIR Filter.
I/Q Splitter / NCO
Stand Alone FFT Processor
( Commercial - PGA
Package )
PDSP16515A C0 GC
( Commercial - Leaded
Chip Carrier )
PDSP16515A B0 AC
( Industrial - PGA
Package )
PDSP16515A B0 GC
( Industrial -
Leaded
Chip Carrier )
PDSP16515A A0 AC
( Military - PGA
Package )
PDSP16515A A0 GC
( Military - Leaded Chip
Carrier )
PDSP16515A/MA/GCPR
( Military - Screened
Leaded Chip Carrier. See separate datasheet for
details )
PDSP16515A C0 AC
The PDSP16515A performs Forward or Inverse Fast
Fourier Transforms on complex or real data sets
containing up to 1024 points. Data and coefficient input
are both represented by 16 bits. Data is expanded
internally to 18 bits and subject to Block Floating Point
arithmetic to preserve a greater dynamic range.
An internal RAM is provided which can hold up to 1024
complex data points. This removes the memory transfer
bottleneck, inherent in building block solutions. Its
organisation allows the PDSP16515A to
simultaneously input new data, transform data stored in
the RAM, and to output previous results. No external
buffering is needed for transforms containing up to 256
points, and the PDSP16515A can be directly connected
to an A/D converter to perform continuous transforms.
The user can choose to overlap data blocks by either
0%, 50%, or 75%. Inputs and outputs are synchronous
to the 45MHz system clock used for internal operations.
A 1024 point complex transform can be completed in
some 87µs, which is equivalent to throughput rates of
500 million operations per second. Multiple devices can
be connected in parallel in order to increase the
sampling rate up to the 45MHz system clock. Six
devices are needed to give the maximum performance
with 1024 point transforms.
Either a Hamming or a Blackman-Harris window
operator can be internally applied to the incoming real or
complex data. The latter gives 67dB side lobe
attenuation. The operator values are calculated
internally and do not require an external ROM nor do
they incur any time penalty.
The increased internal bus size together with block
floating arithmetic produce up to 85dB of noise
rejection.
The device outputs the real and imaginary components
of the frequency bins. These can be directly connected
to the PDSP16330 in order to produce magnitude and
phase values from the complex data.
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ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
