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PDSP16256 参数 Datasheet PDF下载

PDSP16256图片预览
型号: PDSP16256
PDF下载: 下载PDF文件 查看货源
内容描述: 单机FFT处理器 [Stand Alone FFT Processor]
分类和应用:
文件页数/大小: 25 页 / 174 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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PDSP16515A
The active going LFLG edge does not normally have any
system significance, but in the block overlapping modes the
in-active going edge will occur when 50% or 75% of the data
has been loaded. By driving the INEN input on one device with
the LFLG output from a previous device, this edge can be used
to partition data between several devices in a multiple device
system. It can also be used to provide an address marker for
a user defined input buffer, when executing 1024 point
transforms with a single device. It is not needed, however,
when the input buffer is provided by the PDSP16540.
Since there is no external indication of this event, the user
must take care to only allow DEN to go high whilst DAV is
active, if this DAV synchronous mode is needed.
Synchronized Dav Operation
In the DAV synchronised mode the first rising edge of the DOS
clock, after DAV has gone active, must be used to transfer the
first transformed sample from the output pins to the next
system component. It should be noted that the output buffer
will have been primed before the active DAV transition, since
DOS must be a continuous clock, and there is then no delay
before the first output becomes valid. The DAV output can be
used as a clock enable for this next device, and transfers will
continue in normal sequential order until the required data has
been dumped. DAV will then go inactive in response to the last
DOS edge which was used to transfer data to the next device.
This mode of automatically dumping data when it is ready
finds applications in real time data flow systems, and detailed
timing is given in Table 2. It should be noted that the DOS input
MUST be continually present before DAV goes active. If this
is not the case the DAV output will not go active at the correct
time, and the internal output circuitry will not be primed. Once
DAV is active, however, it is possible for DOS to be irregular,
and DEN can be used to inhibit the action of the output strobe
as discussed previously. For the correct operation of the
device the user must ensure that DOS becomes continuous
and DEN remains low once DAV goes in-active.
Dumping Data
Data output is controlled by an output strobe [DOS], a dump
enable signal [DEN], and a Data Available signal [DAV]. The
DAV signal is used to indicate that the internal output buffer
contains transformed data, and the DEN input is used to
control the outputting of that data. The output buffer within the
device is clocked by the DOS input, and must be primed with
a number of DOS strobes (see "user notes - stopping DOS")
once a transform is complete in order to transfer data to the
output pins. DAV will not go active until this priming has
occurred.
The state of the DEN input at the end of a transform is used to
control the transition of the active going edge of the DAV
output with respect to the DOS strobes. The latter are then
used to transfer data from the device to the next system
component. If the DEN input is tied low in a single device
system, the active going DAV transition will be internally
synchronised to the rising edge of a DOS clock. If DEN is not
tied low it must be guaranteed to be low at the end of the
internal transform operation for this synchronization to occur.
1
DOS
T
DD
N
T
DD
DATA O/P
T
LZ
O/P 1
T
DH
O/P 2
T
HZ
S3:0
Scale Tag Value
DAV
T
VD
T
VI
Characteristic
Output Enable Time
Output Disable Time
Data Delay Time ( 30 pf load )
Data Hold Time
DAV active Delay Time ( 30 pf load )
DAV in active Delay Time ( 30 pf load )
Symbol
T
LZ
T
HZ
T
DD
T
DH
T
VD
T
VI
Min
Max
18
18
18
Units
ns
ns
ns
ns
ns
ns
2
1
1
15
15
Table 2. Output Timing with DEN tied low. ( Advanced Data )
9