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ZL30100QDG1 参数 Datasheet PDF下载

ZL30100QDG1图片预览
型号: ZL30100QDG1
PDF下载: 下载PDF文件 查看货源
内容描述: T1 / E1系统同步 [T1/E1 System Synchronizer]
分类和应用: 电信集成电路电信电路
文件页数/大小: 36 页 / 385 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL30100
T1/E1 System Synchronizer
Data Sheet
Features
Supports Telcordia GR-1244-CORE Stratum 4 and
Stratum 4E
Supports ITU-T G.823 and G.824 for 2048 kbit/s and
1544 kbit/s interfaces
Supports ANSI T1.403 and ETSI ETS 300 011 for
ISDN primary rate interfaces
Simple hardware control interface
Accepts two input references and synchronizes to
any combination of 8 kHz, 1.544 MHz, 2.048 MHz,
8.192 MHz or 16.384 MHz inputs
Provides a range of clock outputs: 1.544 MHz,
2.048 MHz, 16.384 MHz and either 4.096 MHz and
8.192 MHz or 32.768 MHz and 65.536 MHz
Hitless reference switching between any
combination of valid input reference frequencies
Provides 5 styles of 8 kHz framing pulses
Holdover frequency accuracy of 1.5 x 10
-7
Lock, Holdover and selectable Out of Range
indication
Selectable loop filter bandwidth of 1.8 Hz or 922 Hz
Ordering Information
ZL30100QDC 64 Pin TQFP Trays
ZL30100QDG1 64 Pin TQFP* Trays, Bake & Drypack
*Pb Free Matte Tin
-40°C to +85°C
February 2006
Less than 0.6 ns
pp
intrinsic jitter on all output
clocks
External master clock source: clock oscillator or
crystal
Applications
Synchronization and timing control for multi-trunk
DS1/E1 systems such as DSLAMs, gateways and
PBXs
Clock and frame pulse source for ST-BUS, GCI
and other time division multiplex (TDM) buses
Line Card synchronization for PDH systems
OSCi OSCo
Master Clock
REF0
REF1
MUX
TIE_CLR
BW_SEL LOCK
OUT_SEL
C2o
C4/C65o
C8/C32o
C16o
F4/F65o
F8/F32o
F16o
DS1
Synthesizer
C1.5o
TIE
Corrector
Circuit
Virtual
Reference
DPLL
E1
Synthesizer
REF_FAIL0
REF_FAIL1
OOR_SEL
REF_SEL
Reference
Monitor
TIE
Corrector
Enable
Mode
Control
Feedback
State Machine
RST
Frequency
Select
MUX
IEEE
1149.1a
TRST
MODE_SEL1:0
HMS
HOLDOVER
TCK TDI
TMS TDO
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.