ZL30111
POTS Line Card PLL
Data Sheet
Features
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Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or
19.44 MHz input
Provides a range of clock outputs: 2.048 MHz,
4.096 MHz and 8.192 MHz
Provides 2 styles of 8 kHz framing pulses
Automatic entry and exit from freerun mode on
reference fail
Provides DPLL lock and reference fail indication
DPLL bandwidth of 922 Hz for all rates of input
reference and 58 Hz for an 8 kHz input reference
Less than 0.6 ns
pp
intrinsic jitter on all output clocks
20 MHz external master clock source: clock
oscillator or crystal
Simple hardware control interface
Ordering Information
ZL30111QDG
ZL30111QDG1
64 Pin TQFP Trays, Bake & Drypack
64 Pin TQFP* Trays, Bake & Drypack
*Pb Free Matte Tin
-40°C to +85°C
January 2007
Applications
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Synchronizer for POTS line cards
Rate convert NTR 8kHz or GPON physical
interface clock to TDM clock
Description
The ZL30111 POTS line card PLL contains a digital
phase-locked loop (DPLL), which provides timing and
synchronization for SLIC/CODEC devices.
The ZL30111 generates TDM clock and framing
signals that are phase locked to the input reference.
It helps ensure system reliability by monitoring its
reference for stability and by maintaining stable
output clocks during short periods when the
reference is unavailable.
REF_FAIL
LOCK
REF
DPLL
Reference
Monitor
Mode
Control
C2o
C4
C8
F4
F8
RST
OSCi
OSCo
State Machine
Master
Clock
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
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Copyright 2007, Zarlink Semiconductor Inc. All Rights Reserved.