ZL30111
2.0
Functional Description
Data Sheet
The ZL30111 POTS line card PLL contains a digital phase-locked loop (DPLL), which provides timing and
synchronization for SLIC/CODEC devices. Figure 1 is a functional block diagram which is described in the
following sections.
2.1
Reference Monitor
The input reference is monitored by two reference monitor blocks. The block diagram of reference monitoring is
shown in Figure 3. The reference frequency is detected and the clock is continuously monitored for two
independent criteria that indicate abnormal behavior of the reference signal, for example; loss of clock or excessive
level of frequency error. To ensure proper operation of the reference monitor circuit, the minimum input pulse
width restriction of 15 nsec must be observed.
•
Reference Frequency Detector (RFD):
This detector determines whether the frequency of the reference
clock is 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz and provides this information to the various monitor
circuits and the phase detector circuit of the DPLL.
Coarse Frequency Monitor (CFM):
This circuit monitors the reference frequency over intervals of
approximately 30
µs
to quickly detect large frequency changes.
Single Cycle Monitor (SCM):
This detector checks the period of a single clock cycle to detect large phase
hits or the complete loss of the clock.
•
•
Reference Frequency
Detector
REF
Coarse Frequency
Monitor
REF_FAIL
OR
Single Cycle
Monitor
Mode select
state machine
DPLL in FreeRun Mode
Figure 3 - Reference Monitor Circuit
Exceeding the thresholds of any of the monitors forces the corresponding REF_FAIL pin to go high. The single
cycle and coarse frequency failure flags force the DPLL into FreeRun mode.
8
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
