ZL30120
SONET/SDH/Ethernet
Multi-Rate Line Card Synchronizer
Data Sheet
May 2006
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Ordering Information
ZL30120GGG
100 Pin CABGA
Trays
ZL30120GGG2 100 Pin CABGA** Trays
**Pb Free Tin/Silver/Copper
-40
o
C to +85
o
C
•
Provides two DPLLs which have independent
modes of operation (locked, free-run, holdover)
and optional hitless reference switching.
Flexible input reference monitoring automatically
disqualifies references based on frequency and
phase irregularities
Provides 3 sync inputs for output frame pulse
alignment
Generates several styles of output frame pulses
with selectable pulse width, polarity, and frequency
Configurable input to output delay, and output to
output phase alignment
Supports IEEE 1149.1 JTAG Boundary Scan
Features
•
Synchronizes with standard telecom system
references and synthesizes a wide variety of
protected telecom line interface clocks that are
compliant with Telcordia GR-1244-CORE, GR-253-
CORE, ITU-T G.813, and compatible with ITU-T
G.8261 (formerly G.pactiming)
Internal low jitter APLL provides SONET/SDH
clocks including 6.48 MHz, 19.44 MHz, 38.88 MHz,
51.84 MHz and 77.76 MHz, or 25 MHz and 50 MHz
Synchronous Ethernet output clocks
Programmable output synthesizers (P0, P1)
generate general purpose clock frequencies from
any multiple of 8 kHz up to 100 MHz
Jitter performance of <8 ps RMS on the low jitter
APLL outputs, and <20 ps RMS on the
programmable synthesizer outputs.
Provides 8 reference inputs which support clock
frequencies with any multiples of 8 kHz up to
77.76 MHz in addition to 2 kHz
•
•
•
•
•
•
•
•
•
trst_b tck tdi tms
tdo
dpll2_ref
dpll1_hs_en
dpll1_lock dpll1_holdover
osco
osci
Master
Clock
IEEE 1449.1
JTAG
ref
DPLL2
P0
Synthesizer
P1
Synthesizer
p0_clk0
p0_clk1
p0_fp0
p0_fp1
p1_clk0
p1_clk1
apll_clk0
apll_clk1
apll_fp0
apll_fp1
ref0
ref1
ref2
ref3
ref4
ref5
ref6
ref7
sync0
sync1
sync2
ref7:0
ref
Low Jitter
APLL
DPLL1
sync2:0
Reference
Monitors
ref_&_sync_status
sync
fb_clk/fp
Feedback
Synthesizer
fb_clk
int_b
SPI Interface
Controller &
State Machine
sck
si
so
cs_b
rst_b
dpll1_mod_sel1:0
apll_filter
filter_ref0
filter_ref1
Figure 1 - Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved.
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