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ZL30122 参数 Datasheet PDF下载

ZL30122图片预览
型号: ZL30122
PDF下载: 下载PDF文件 查看货源
内容描述: SONET / SDH的低抖动线路卡同步器 [SONET/SDH Low Jitter Line Card Synchronizer]
分类和应用:
文件页数/大小: 23 页 / 260 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL30122
SONET/SDH
Low Jitter Line Card Synchronizer
Data Sheet
May 2006
A full Design Manual is available to qualified customers.
To
register,
please
send
an
email
to
TimingandSync@Zarlink.com.
Ordering Information
ZL30122GGG
64 Pin CABGA
Trays
ZL30122GGG2 64 Pin CABGA*
Trays
*Pb Free Tin/Silver/Copper
-40
o
C to +85
o
C
Provides 3 reference inputs which support clock
frequencies with any multiples of 8 kHz up to
77.76 MHz in addition to 2 kHz
Provides 3 sync inputs for output frame pulse
alignment
Generates several styles of output frame pulses
with selectable pulse width, polarity, and frequency
Configurable input to output delay, and output to
output phase alignment
Flexible input reference monitoring automatically
disqualifies references based on frequency and
phase irregularities
Supports IEEE 1149.1 JTAG Boundary Scan
Features
Synchronizes with standard telecom system
references and synthesizes a wide variety of
protected telecom line interface clocks that are
compliant with Telcordia GR-253-CORE and ITU-T
G.813
Internal APLL provides standard output clock
frequencies up to 622.08 MHz with jitter < 3 ps
RMS suitable for GR-253-CORE OC-12 and G.813
STM-16 interfaces
Programmable output synthesizer generates clock
frequencies from any multiple of 8 kHz up to
77.76 MHz in addition to 2 kHz
Digital Phase Locked-Loop (DPLL) provides all the
features necessary for generating SONET/SDH
compliant clocks including automatic hitless
reference switching, automatic mode selection
(locked, free-run, holdover), and selectable loop
bandwidth
trst_b tck tdi tms
tdo
dpll_lock
dpll_holdover
diff_en
osco
osci
Master
Clock
IEEE 1449.1
JTAG
ref0
ref1
ref2
ref2:0
ref
diff_clk_p/n
SONET/SDH
APLL
sdh_clk
sdh_fp
p_clk
p_fp
DPLL
sync0
sync1
sync2
sync2:0
Reference
Monitors
ref_&_sync_status
sync
Programmable
Synthesizer
int_b
SPI Interface
Controller &
State Machine
sck
si
so
cs_b
rst_b
dpll_mod_sel
sdh_filter
filter_ref0
filter_ref1
Figure 1 - Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved.