ZL30402
Pin Description
Pin #
1
2-5
6
7-8
9
Name
IC
A1-A4
GND
A5-A6
FCS
Description
Internal Connection.
Leave unconnected.
Data Sheet
Address 1 to 4
(5 V tolerant input). Address inputs for the parallel processor
interface. Connect to ground in Hardware Control.
Ground.
Negative power supply.
Address 5 to 6
(5 V tolerant input). Address inputs for the parallel processor
interface. Connect to ground in Hardware Control.
Filter Characteristic Select (Input).
In Hardware Control, FCS selects the
filtering characteristics of the ZL30402. Set this pin high to have a loop filter
corner frequency of 0.1 Hz and limit the phase slope to 885 ns per second. Set
this pin low to have corner frequency of 1.1 Hz and limit the phase slope to
41 ns per 1.326 ms. Connect to ground in Software Control. This pin is
internally pulled down to GND.
Positive Power Supply.
Ground.
Frame Pulse ST-BUS 8.192 Mb/s
(CMOS tristate output). This is an 8 kHz,
61 ns wide, active low framing pulse, which marks beginning of a ST-BUS
frame. This frame pulse is typically used for ST-BUS operation at 8.192 Mb/s
Clock 16.384 MHz
(CMOS tristate output). This clock is used for ST-BUS
operation at 8.192 Mb/s.
Clock 8.192 MHz
(CMOS tristate output). This clock is used for ST-BUS
operation at 8.192 Mb/s.
Clock 4.096 MHz
(CMOS tristate output). This clock is used for ST-BUS
operation at 2.048 Mb/s.
Clock 2.048 MHz
(CMOS tristate output). This clock is used for ST-BUS
operation at 2.048 Mb/s.
Frame Pulse ST-BUS 2.048 Mb/s
(CMOS tristate output). This is an 8 kHz,
244 ns, active low framing pulse, which marks the beginning of a ST-BUS
frame. This is typically used for ST-BUS operation at 2.048 Mb/s and
4.096 Mb/s.
Mode Select 1
(Input). The MS1 and MS2 pins select the ZL30402 mode of
operation (Normal, Holdover or Free-run), see Table 1 on page 18 for details.
The logic level at this input is sampled by the rising edge of the F8o frame
pulse. Connect to ground in Software Control.
Mode Select 2
(Input). The MS2 and MS1 pins select the ZL30402 mode of
operation (Normal, Holdover or Free-run), see Table 1 on page 18 for details.
The logic level at this input is sampled by the rising edge of the F8o frame
pulse. Connect to ground in Software Control.
10
11
12
VDD
GND
F16o
13
14
15
16
17
C16o
C8o
C4o
C2o
F0o
18
MS1
19
MS2
7
Zarlink Semiconductor Inc.
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