ZL38001
AEC for Analog Hands-Free
Communication
Data Sheet
Zarlink has introduced a new generation family of
AEC (ZL38002 and ZL38004). Zarlink recommends
these products for new designs.
October 2006
Features
•
•
•
•
•
•
•
•
•
•
•
Contains two echo cancellers: 112 ms acoustic
echo canceller + 16 ms line echo canceller
Works with low cost voice codec. ITU-T G.711 or
signed mag
µ/A-Law,
or linear 2’s comp
Each port may operate in different format
Advanced NLP design - full duplex speech with
no switched loss on audio paths
Fast re-convergence time: tracks changing echo
environment quickly
Adaptation algorithm converges even during
Double-Talk
Designed for exceptional performance in high
background noise environments
Provides protection against narrow-band signal
divergence
Howling prevention stops uncontrolled oscillation
in high loop gain conditions
Offset nulling of all PCM channels
Serial micro-controller interface
Ordering Information
ZL38001DGA
36 Pin QSOP Tubes
ZL38001QDC
48 Pin TQFP
Trays
ZL38001QDG1 48 Pin TQFP* Trays, Bake & Drypack
ZL38001DGF1 36 Pin SSOP* Tape & Reel,
Bake & Drypack
ZL38001DGE1 36 Pin SSOP* Tubes, Bake & Drypack
*Pb Free Matte Tin
-40°C to +85°C
•
•
•
•
•
•
•
•
•
•
ST-BUS, GCI, or variable-rate SSI PCM interfaces
User gain control provided for speaker path
(-24 dB to +48 dB in 3 dB steps)
18 dB gain at Sout to compensate for high ERL
environments
AGC on speaker path
Handles up to 0 dB acoustic echo return loss
Transparent data transfer and mute options
20 MHz master clock operation
Low power mode during PCM Bypass
Bootloadable for future factory software upgrades
2.7 V to 3.6 V supply voltage; 5 V-tolerant inputs
Sin
MD1
µ
/A-Law/
Linear
Offset
Null
+
Limiter
+
-
S
2
ADV
NLP
Program
RAM
S
3
Program
ROM
18dB
Gain
Linear/
µ/A-Law
Sout
DATA1
ACOUSTIC ECHO PATH
NBSD
S
1
Micro
Interface
DATA2
CONTROL
UNIT
Adaptive
Filter
Double
Talk
Detector
R
3
R
2
ADV
NLP
Line ECho Path
PORT 1
PORT 2
Adaptive
Filter
NBSD
Howling
Controller
R
1
MD2
Rout
L
inear/
µ
/A-Law
Limiter
SCLK
-24 -> +21 dB
AGC
User
Gain
-
CS
+
+
Offset
Null
µ
/A-Law/
Linear
Rin
VDD
VSS
RESET
FORMAT
ENA2
ENA1
LAW
F0i
BCLK/C4i
MCLK
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
