ZL38003
AEC with Noise Reduction & Codecs for
Digital Hands-Free Communication
Data Sheet
A full Design Manual is available to qualified
customers. To register, please send an email to
VoiceProcessing@Zarlink.com.
May 2006
Ordering Information
ZL38003GMG 81 Ball CBGA Trays, Bake & Drypack
ZL38003GMG2 81 Ball CBGA** Trays, Bake & Drypack
**Pb Free Tin/Silver/Copper
-40°C to +85°C
Features
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Handles up to -6 dB acoustic echo return loss
127 ms acoustic echo canceller
Provides up to 12 dB of Noise Reduction
Operate in two modes, Dual Analog mode and
single Analog mode (other port is digital PCM)
PCM Data Formats in single Port mode- 16-bit
Linear, companded ITU-T A-law or U-law
Advanced NLP design - full duplex speech with
no switched loss on audio paths
Tracks changing echo environment quickly
Adaptation algorithm converges even during
Double-Talk
Designed for performance in high background
noise environments
Provides protection against narrow-band signal
divergence
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Howling prevention eliminates uncontrolled
oscillation in high loop gain conditions
AGC on speaker path
Transparent data transfer and mute options
Boot loadable for future factory software upgrades
Serial micro-controller interface
Two 16 bit linear ACD and DAC that meet ITU-T
G.711/712 recommendations
Four Audio TX/RX Interfaces
Differential Microphone Inputs
Programmable Bias Voltage Output for Electret
microphones
Microphone Presence Detection, Microphone
Mute
SCLK
CS_CODEC
CS_AEC
DATA1
DATA2
FPi
C4i
Rin
EAR
Serial
Microport
Interface
G.712
Codec
#1
Rout/Sout
AEC
Sin/Rin
Crosspoint
Audio Interface
G.712
Codec
#0
#1
EAR
MIC
Audio Interface
#3
MIC
BIAS
MICDET
PCM
Timing
EAR
Audio Interface
#2
MIC
BIAS
MICDET
Sout
MCLK
RESETB
AUXTONE
Audio Interface
#0
EAR/SPEAKER
MIC
BIAS
Figure 1 - Block Diagram
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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2005-2006, Zarlink Semiconductor Inc. All Rights Reserved.
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